[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Luke Lau via llvm-commits]

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@@ -10760,16 +10762,38 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
   if (!VL)
     VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
 
-  unsigned IntID =
-      IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+  SDValue Index;
+  if (!IsUnmasked && IsExpandingLoad) {
+    MVT IndexVT = ContainerVT;
+    if (ContainerVT.isFloatingPoint())
+      IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+    if (Subtarget.isRV32() && IndexVT.getVectorElementType().bitsGT(XLenVT))
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
+
+    Index = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
+                        DAG.getConstant(Intrinsic::riscv_viota, DL, XLenVT),
+                        DAG.getUNDEF(IndexVT), Mask, VL);
+    if (uint64_t EltSize = ContainerVT.getScalarSizeInBits(); EltSize > 8)
+      Index = DAG.getNode(RISCVISD::SHL_VL, DL, IndexVT, Index,
+                          DAG.getConstant(Log2_64(EltSize / 8), DL, IndexVT),
+                          DAG.getUNDEF(IndexVT), Mask, VL);
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lukel97 wrote:

Ah ok, was worth a shot

https://github.com/llvm/llvm-project/pull/101954