[llvm] [BOLT] Refactor AArch64 Relocation Print (PR #101895)

[via llvm-commits]

https://github.com/linsinan1995 created https://github.com/llvm/llvm-project/pull/101895

AArch64 relocations are not sequentially numbered (more details on llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def), so directly mapping the relocation type to its name can trigger a debug assertion `assert(Type < ArrayRef(AArch64RelocNames).size())`.

Refactor the AArch64 relocation print based on how RISC-V arch does.

>From 43185dac19eb5d27f8553275a56d7ac642b70b5a Mon Sep 17 00:00:00 2001
From: Sinan Lin <sinan.lin at linux.alibaba.com>
Date: Sun, 4 Aug 2024 23:37:02 +0800
Subject: [PATCH] [BOLT] Refactor AArch64 Relocation Print

AArch64 relocations are not sequentially numbered (more details on
llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def), so directly
mapping the relocation type to its name can trigger a debug
assertion `assert(Type < ArrayRef(AArch64RelocNames).size())`.

Refactor the AArch64 relocation print based on how RISC-V arch does.
---
 bolt/lib/Core/Relocation.cpp | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/bolt/lib/Core/Relocation.cpp b/bolt/lib/Core/Relocation.cpp
index 4e888a5b147ac..48362191fafe2 100644
--- a/bolt/lib/Core/Relocation.cpp
+++ b/bolt/lib/Core/Relocation.cpp
@@ -1071,13 +1071,18 @@ void Relocation::print(raw_ostream &OS) const {
     break;
 
   case Triple::aarch64:
-    static const char *const AArch64RelocNames[] = {
-#define ELF_RELOC(name, value) #name,
+    // AArch64 relocations are not sequentially numbered so we cannot use an
+    // array
+    switch (Type) {
+    default:
+      llvm_unreachable("illegal AArch64 relocation");
+#define ELF_RELOC(name, value)                                                 \
+  case value:                                                                  \
+    OS << #name;                                                               \
+    break;
 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
 #undef ELF_RELOC
-    };
-    assert(Type < ArrayRef(AArch64RelocNames).size());
-    OS << AArch64RelocNames[Type];
+    }
     break;
 
   case Triple::riscv64: