[llvm] [CodeGen] Construct SmallVector with ArrayRef (NFC) (PR #101841)
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Sat Aug 3 11:44:36 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-debuginfo
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-llvm-regalloc
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/101841.diff
14 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h (+3-3)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h (+1-2)
- (modified) llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp (+1-1)
- (modified) llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h (+2-4)
- (modified) llvm/lib/CodeGen/GlobalISel/CallLowering.cpp (+1-1)
- (modified) llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (+7-7)
- (modified) llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp (+1-2)
- (modified) llvm/lib/CodeGen/LiveIntervals.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineScheduler.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+2-3)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+1-1)
- (modified) llvm/lib/CodeGen/ShrinkWrap.cpp (+1-2)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
index bb3be3e2b4f98..6f79313c41862 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -54,7 +54,7 @@ class CallLowering {
BaseArgInfo(Type *Ty,
ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
bool IsFixed = true)
- : Ty(Ty), Flags(Flags.begin(), Flags.end()), IsFixed(IsFixed) {}
+ : Ty(Ty), Flags(Flags), IsFixed(IsFixed) {}
BaseArgInfo() : Ty(nullptr), IsFixed(false) {}
};
@@ -81,8 +81,8 @@ class CallLowering {
ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
bool IsFixed = true, const Value *OrigValue = nullptr)
- : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()),
- OrigValue(OrigValue), OrigArgIndex(OrigIndex) {
+ : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs), OrigValue(OrigValue),
+ OrigArgIndex(OrigIndex) {
if (!Regs.empty() && Flags.empty())
this->Flags.push_back(ISD::ArgFlagsTy());
// FIXME: We should have just one way of saying "no register".
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h b/llvm/include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h
index b42deb01f8d09..cad2216db34fe 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h
@@ -69,8 +69,7 @@ class GISelObserverWrapper : public MachineFunction::Delegate,
public:
GISelObserverWrapper() = default;
- GISelObserverWrapper(ArrayRef<GISelChangeObserver *> Obs)
- : Observers(Obs.begin(), Obs.end()) {}
+ GISelObserverWrapper(ArrayRef<GISelChangeObserver *> Obs) : Observers(Obs) {}
// Adds an observer.
void addObserver(GISelChangeObserver *O) { Observers.push_back(O); }
// Removes an observer from the list and does nothing if observer is not
diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
index 4957f70b23f08..05bc453d158d6 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
@@ -136,7 +136,7 @@ class AppleAccelTableWriter : public AccelTableWriter {
const SmallVector<Atom, 4> Atoms;
HeaderData(ArrayRef<Atom> AtomList, uint32_t Offset = 0)
- : DieOffsetBase(Offset), Atoms(AtomList.begin(), AtomList.end()) {}
+ : DieOffsetBase(Offset), Atoms(AtomList) {}
void emit(AsmPrinter *Asm) const;
#ifndef NDEBUG
diff --git a/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h b/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h
index 069766ccddc2f..5358f7b54f411 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h
@@ -118,13 +118,11 @@ class DbgValueLoc {
public:
DbgValueLoc(const DIExpression *Expr, ArrayRef<DbgValueLocEntry> Locs)
- : Expression(Expr), ValueLocEntries(Locs.begin(), Locs.end()),
- IsVariadic(true) {}
+ : Expression(Expr), ValueLocEntries(Locs), IsVariadic(true) {}
DbgValueLoc(const DIExpression *Expr, ArrayRef<DbgValueLocEntry> Locs,
bool IsVariadic)
- : Expression(Expr), ValueLocEntries(Locs.begin(), Locs.end()),
- IsVariadic(IsVariadic) {
+ : Expression(Expr), ValueLocEntries(Locs), IsVariadic(IsVariadic) {
#ifndef NDEBUG
assert(Expr->isValid() ||
!any_of(Locs, [](auto LE) { return LE.isLocation(); }));
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index d16585b5650a7..513914d3218fb 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -436,7 +436,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
if (PartLLT.isVector()) {
assert(OrigRegs.size() == 1);
- SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
+ SmallVector<Register> CastRegs(Regs);
// If PartLLT is a mismatched vector in both number of elements and element
// size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 7eb6cd4e0d798..925a1c7cf6aac 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -646,7 +646,7 @@ MachineInstrBuilder MachineIRBuilder::buildMergeValues(const DstOp &Res,
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
+ SmallVector<SrcOp, 8> TmpVec(Ops);
assert(TmpVec.size() > 1);
return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
}
@@ -657,7 +657,7 @@ MachineIRBuilder::buildMergeLikeInstr(const DstOp &Res,
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
+ SmallVector<SrcOp, 8> TmpVec(Ops);
assert(TmpVec.size() > 1);
return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);
}
@@ -685,7 +685,7 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
+ SmallVector<DstOp, 8> TmpVec(Res);
assert(TmpVec.size() > 1);
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
}
@@ -702,7 +702,7 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
+ SmallVector<DstOp, 8> TmpVec(Res);
assert(TmpVec.size() > 1);
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
}
@@ -712,7 +712,7 @@ MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
+ SmallVector<SrcOp, 8> TmpVec(Ops);
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
}
@@ -739,7 +739,7 @@ MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
+ SmallVector<SrcOp, 8> TmpVec(Ops);
if (TmpVec[0].getLLTTy(*getMRI()).getSizeInBits() ==
Res.getLLTTy(*getMRI()).getElementType().getSizeInBits())
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
@@ -789,7 +789,7 @@ MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
- SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
+ SmallVector<SrcOp, 8> TmpVec(Ops);
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 20d5b2602df12..a69dbbbbdab3c 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -252,8 +252,7 @@ class TransferTracker {
DbgValueProperties Properties;
UseBeforeDef(ArrayRef<DbgOp> Values, DebugVariableID VarID,
const DbgValueProperties &Properties)
- : Values(Values.begin(), Values.end()), VarID(VarID),
- Properties(Properties) {}
+ : Values(Values), VarID(VarID), Properties(Properties) {}
};
/// Map from instruction index (within the block) to the set of UseBeforeDefs
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 33270807f260a..d879a7c1fb37e 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -1681,7 +1681,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
Indexes->repairIndexesInRange(MBB, Begin, End);
// Make sure a live interval exists for all register operands in the range.
- SmallVector<Register> RegsToRepair(OrigRegs.begin(), OrigRegs.end());
+ SmallVector<Register> RegsToRepair(OrigRegs);
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index a8a17101b9c92..7a3cf96ccffe0 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1742,8 +1742,8 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps,
int64_t Offset, bool OffsetIsScalable, LocationSize Width)
- : SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset),
- Width(Width), OffsetIsScalable(OffsetIsScalable) {}
+ : SU(SU), BaseOps(BaseOps), Offset(Offset), Width(Width),
+ OffsetIsScalable(OffsetIsScalable) {}
static bool Compare(const MachineOperand *const &A,
const MachineOperand *const &B) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 060e66175d965..20b3ca21ef8a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -25241,7 +25241,7 @@ static SDValue combineShuffleToZeroExtendVectorInReg(ShuffleVectorSDNode *SVN,
if (!VT.isInteger() || IsBigEndian)
return SDValue();
- SmallVector<int, 16> Mask(SVN->getMask().begin(), SVN->getMask().end());
+ SmallVector<int, 16> Mask(SVN->getMask());
auto ForEachDecomposedIndice = [NumElts, &Mask](auto Fn) {
for (int &Indice : Mask) {
if (Indice < 0)
@@ -25444,8 +25444,7 @@ static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf,
if (!MinNonUndefIdx)
return DAG.getUNDEF(VT); // All undef - result is undef.
assert(*MinNonUndefIdx < NumElts && "Expected valid element index.");
- SmallVector<int, 8> SplatMask(Shuf->getMask().begin(),
- Shuf->getMask().end());
+ SmallVector<int, 8> SplatMask(Shuf->getMask());
for (int &Idx : SplatMask) {
if (Idx < 0)
continue; // Passthrough sentinel indices.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 41fcc9afe4e90..edebb5ee87001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -3577,7 +3577,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_ATOMIC_STORE(SDNode *N,
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo) {
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
- SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
+ SmallVector<SDValue> NewOps(N->ops());
SDValue Op = N->getOperand(OpNo);
NewOps[OpNo] = GetSoftPromotedHalf(Op);
SDValue NewNode =
@@ -3592,7 +3592,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_PATCHPOINT(SDNode *N,
unsigned OpNo) {
assert(OpNo >= 7);
- SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
+ SmallVector<SDValue> NewOps(N->ops());
SDValue Op = N->getOperand(OpNo);
NewOps[OpNo] = GetSoftPromotedHalf(Op);
SDValue NewNode =
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index b1ada66aa9aeb..a342d04ce4c47 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2704,7 +2704,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
- SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
+ SmallVector<SDValue> NewOps(N->ops());
SDValue Operand = N->getOperand(OpNo);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Operand.getValueType());
NewOps[OpNo] = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Operand);
@@ -2713,7 +2713,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
assert(OpNo >= 7);
- SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());
+ SmallVector<SDValue> NewOps(N->ops());
SDValue Operand = N->getOperand(OpNo);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Operand.getValueType());
NewOps[OpNo] = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Operand);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index b3ed7f78eb68e..a9f2be5726649 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10032,7 +10032,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
// Copy from an SDUse array into an SDValue array for use with
// the regular getNode logic.
- SmallVector<SDValue, 8> NewOps(Ops.begin(), Ops.end());
+ SmallVector<SDValue, 8> NewOps(Ops);
return getNode(Opcode, DL, VT, NewOps);
}
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 239572bf773e8..b9f376a5af794 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -440,8 +440,7 @@ static bool
isSaveReachableThroughClean(const MachineBasicBlock *SavePoint,
ArrayRef<MachineBasicBlock *> CleanPreds) {
DenseSet<const MachineBasicBlock *> Visited;
- SmallVector<MachineBasicBlock *, 4> Worklist(CleanPreds.begin(),
- CleanPreds.end());
+ SmallVector<MachineBasicBlock *, 4> Worklist(CleanPreds);
while (!Worklist.empty()) {
MachineBasicBlock *CleanBB = Worklist.pop_back_val();
if (CleanBB == SavePoint)
``````````
</details>
https://github.com/llvm/llvm-project/pull/101841
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