[llvm] [DAG] Remove OneUse restriction when folding (shl (add x, c1), c2) (PR #101294)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 3 05:15:20 PDT 2024
https://github.com/LiqinWeng updated https://github.com/llvm/llvm-project/pull/101294
>From eb292417cf0528e7c3f59df7637133148add3e2a Mon Sep 17 00:00:00 2001
From: LiqinWeng <liqin.weng at spacemit.com>
Date: Sat, 3 Aug 2024 19:13:35 +0800
Subject: [PATCH 1/2] [Test] Pre-submit tests for #101294
---
llvm/test/CodeGen/RISCV/add_shl_constant.ll | 62 +++++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/add_shl_constant.ll
diff --git a/llvm/test/CodeGen/RISCV/add_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_shl_constant.ll
new file mode 100644
index 0000000000000..59bfdfef8bed7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/add_shl_constant.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32 %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64 %s
+
+define i32 @add_shl_oneUse(i32 %x, i32 %y) nounwind {
+; RV32-LABEL: add_shl_oneUse:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: addi a0, a0, 984
+; RV32-NEXT: ret
+;
+; RV64-LABEL: add_shl_oneUse:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: addiw a0, a0, 984
+; RV64-NEXT: ret
+ %add.0 = add i32 %x, 123
+ %shl = shl i32 %add.0, 3
+ %add.1 = add i32 %shl, %y
+ ret i32 %add.1
+}
+
+define void @add_shl_addmoreOneUse_in_store(ptr %array1, i32 %a, i32 %b) {
+; RV32-LABEL: add_shl_addmoreOneUse_in_store:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi a3, a1, 5
+; RV32-NEXT: slli a4, a3, 2
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: sw a2, 0(a4)
+; RV32-NEXT: slli a1, a1, 2
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: sw a2, 24(a0)
+; RV32-NEXT: sw a3, 140(a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: add_shl_addmoreOneUse_in_store:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: addiw a3, a1, 5
+; RV64-NEXT: slli a4, a3, 2
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: sw a2, 0(a4)
+; RV64-NEXT: sext.w a1, a1
+; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: sw a2, 24(a0)
+; RV64-NEXT: sw a3, 140(a0)
+; RV64-NEXT: ret
+entry:
+ %add = add nsw i32 %a, 5
+ %arrayidx = getelementptr inbounds i32, ptr %array1, i32 %add
+ store i32 %b, ptr %arrayidx
+ %0 = getelementptr i32, ptr %array1, i32 %a
+ %arrayidx3 = getelementptr i8, ptr %0, i32 24
+ store i32 %b, ptr %arrayidx3
+ %arrayidx5 = getelementptr i8, ptr %0, i32 140
+ store i32 %add, ptr %arrayidx5
+ ret void
+}
>From 1ab5846fbf6e61a2876366f425bad15c982f1767 Mon Sep 17 00:00:00 2001
From: LiqinWeng <liqin.weng at spacemit.com>
Date: Sat, 3 Aug 2024 20:14:27 +0800
Subject: [PATCH 2/2] [DAGCombine] Remove OneUse restriction when folding (shl
(add x, c1), c2)
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 34 +++++++++++++------
llvm/test/CodeGen/RISCV/add_shl_constant.ll | 4 +--
.../CodeGen/RISCV/riscv-shifted-extend.ll | 16 ++++-----
3 files changed, 30 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b35d08b327ef3..5c9001f22cadc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10070,17 +10070,29 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// Variant of version done on multiply, except mul by a power of 2 is turned
// into a shift.
if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
- N0->hasOneUse() && TLI.isDesirableToCommuteWithShift(N, Level)) {
- SDValue N01 = N0.getOperand(1);
- if (SDValue Shl1 =
- DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, {N01, N1})) {
- SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
- AddToWorklist(Shl0.getNode());
- SDNodeFlags Flags;
- // Preserve the disjoint flag for Or.
- if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
- Flags.setDisjoint(true);
- return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
+ TLI.isDesirableToCommuteWithShift(N, Level)) {
+ // ST will optimize constant Offset extraction, so when AddNode
+ // is used by ST, it can still complete the folding optimization
+ // operation performed above.
+ bool canOptAwlays = false;
+ if (!N0.hasOneUse() && N0.getOpcode() == ISD::ADD) {
+ for (SDNode *Use : N0->uses())
+ if (isa<StoreSDNode>(Use))
+ canOptAwlays = true;
+ }
+ if (N0.hasOneUse() || canOptAwlays) {
+ SDValue N01 = N0.getOperand(1);
+ if (SDValue Shl1 =
+ DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, {N01, N1})) {
+ SDValue Shl0 =
+ DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
+ AddToWorklist(Shl0.getNode());
+ SDNodeFlags Flags;
+ // Preserve the disjoint flag for Or.
+ if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
+ Flags.setDisjoint(true);
+ return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
+ }
}
}
diff --git a/llvm/test/CodeGen/RISCV/add_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_shl_constant.ll
index 59bfdfef8bed7..2808faf784f73 100644
--- a/llvm/test/CodeGen/RISCV/add_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_shl_constant.ll
@@ -28,11 +28,9 @@ define void @add_shl_addmoreOneUse_in_store(ptr %array1, i32 %a, i32 %b) {
; RV32-LABEL: add_shl_addmoreOneUse_in_store:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a1, 5
-; RV32-NEXT: slli a4, a3, 2
-; RV32-NEXT: add a4, a0, a4
-; RV32-NEXT: sw a2, 0(a4)
; RV32-NEXT: slli a1, a1, 2
; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: sw a2, 20(a0)
; RV32-NEXT: sw a2, 24(a0)
; RV32-NEXT: sw a3, 140(a0)
; RV32-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll b/llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
index 957f44f9f669d..3ffbcff54baca 100644
--- a/llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s
-define void @test(ptr nocapture noundef writeonly %array1, i32 noundef signext %a, i32 noundef signext %b) {
+define void @test(ptr %array1, i32 signext %a, i32 signext %b) {
; RV64-LABEL: test:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addiw a3, a1, 5
@@ -31,7 +31,7 @@ entry:
}
; test of jumpping, find add's operand has one more use can simplified
-define void @test1(ptr nocapture noundef %array1, i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %x) {
+define void @test1(ptr %array1, i32 signext %a, i32 signext %b, i32 signext %x) {
; RV64-LABEL: test1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addiw a4, a1, 5
@@ -66,15 +66,13 @@ entry:
ret void
}
-define void @test2(ptr nocapture noundef writeonly %array1, i64 noundef %a, i64 noundef %b) local_unnamed_addr #0 {
+define void @test2(ptr %array1, i64 %a, i64 %b) {
; RV64-LABEL: test2:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a3, a1, 5
-; RV64-NEXT: slli a4, a3, 3
-; RV64-NEXT: add a4, a0, a4
-; RV64-NEXT: sd a2, 0(a4)
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: sd a2, 40(a0)
; RV64-NEXT: sd a2, 48(a0)
; RV64-NEXT: sd a3, 280(a0)
; RV64-NEXT: ret
@@ -91,7 +89,7 @@ entry:
ret void
}
-define void @test3(ptr nocapture noundef %array1, i64 noundef %a, i64 noundef %b, i64 noundef %x) {
+define void @test3(ptr %array1, i64 %a, i64 %b, i64 %x) {
; RV64-LABEL: test3:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a4, a1, 5
@@ -100,11 +98,9 @@ define void @test3(ptr nocapture noundef %array1, i64 noundef %a, i64 noundef %b
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a5, a2
; RV64-NEXT: .LBB3_2: # %entry
-; RV64-NEXT: slli a2, a4, 3
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: sd a5, 0(a2)
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: sd a5, 40(a0)
; RV64-NEXT: sd a5, 48(a0)
; RV64-NEXT: sd a4, 280(a0)
; RV64-NEXT: ret
More information about the llvm-commits
mailing list