[llvm] [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (PR #101751)

[Craig Topper via llvm-commits]

topperc wrote:

> This patch breaks zext pattern:
> 
> ```
> ; bin/llc -mtriple=riscv64 test.ll -o -
> define i32 @func0000000000000000(i32 signext %0, i16 signext %1) nounwind {
> entry:
>   %2 = sdiv i16 %1, 2
>   %3 = zext i16 %2 to i32
>   %4 = add i32 %3, %0
>   ret i32 %4
> }
> ```
> 
> Before:
> 
> ```
> func0000000000000000:
>         slli    a2, a1, 48
>         srli    a2, a2, 63
>         add     a1, a1, a2
>         slli    a1, a1, 48
>         srai    a1, a1, 48
>         slli    a1, a1, 47
>         srli    a1, a1, 48
>         addw    a0, a1, a0
>         ret
> ```
> 
> After:
> 
> ```
> func0000000000000000:
>         slli    a2, a1, 48
>         srli    a2, a2, 63
>         add     a1, a1, a2
>         slli    a1, a1, 48
>         srai    a1, a1, 49
>         lui     a2, 16
>         addi    a2, a2, -1
>         and     a1, a1, a2
>         addw    a0, a1, a0
>         ret
> ```
> 
> `and X, 2^16-1` can be lowered to `(X << 48) u>> 48`.

Thanks. I think I have an idea how to fix it. We can do this https://alive2.llvm.org/ce/z/kUowrW

https://github.com/llvm/llvm-project/pull/101751