[llvm] [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (PR #101751)

[Craig Topper via llvm-commits]

topperc wrote:

Adding a one use check fixed most of the regressions I was seeing

https://github.com/llvm/llvm-project/pull/101751