[llvm] [AMDGPU] Always lower s/udiv64 by constant to MUL (PR #100723)

[Fangrui Song via llvm-commits]

MaskRay wrote:

Reverted
At llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6411
```
getOperationAction(ISD::SDIV, MVT::v4i32) == Expand
getOperationAction(ISD::SDIVREM, MVT::i32) == Custom

TLI.getTypeAction(*DAG.getContext(), MVT::v4i64) == TargetLoweringBase::TypeSplitVector
// llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp assertion failure
```

The `LegalizeTypeAction` of `ISD::SRL` for MVT::v4i64 is `TypeSplitVector`, triggering an assertion failure at
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:967

> `assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || ...


https://github.com/llvm/llvm-project/pull/100723