[llvm] [AMDGPU] Always lower s/udiv64 by constant to MUL (PR #100723)

[Fangrui Song via llvm-commits]

MaskRay wrote:

Heads up: This patch also affected ARM, which might cause a SelectionDAG issue for a Halide use case.

```
LLVM ERROR: Cannot select: 0x7339ffda0770: v4i32 = truncate 0x7339ffda0700
  0x7339ffda0700: v4i64 = srl 0x7339ffd8f620, 0x7339ffd8fc40
    0x7339ffd8f620: v4i64 = mul 0x7339ffda03f0, 0x7339ffd8f540
      0x7339ffda03f0: v4i64 = zero_extend 0x7339ffd74690
        0x7339ffd74690: v4i32 = add 0x7339ffd74a80, 0x7339ffaf42a0
          0x7339ffd74a80: v4i32 = add 0x7339ffd747e0, 0x7339ffd745b0
            0x7339ffd747e0: v4i32 = add 0x7339ffd8fa80, 0x7339ffd74620
              0x7339ffd8fa80: v4i32 = ARMISD::VMULLu 0x7339ffda00e0, 0x7339ffda0000
                0x7339ffda00e0: v4i16 = extract_subvector 0x7339ffaf40e0, Constant:i32<0>
                  0x7339ffaf40e0: v8i16,ch = load<(load (s64) from %stack.2), zext from v8i8> 0x7339ffaf4070, FrameIndex:i32<2>, undef:i32
...
```

https://github.com/llvm/llvm-project/pull/100723