[llvm] [SPIR-V] Improve test suite pass rate when expensive checks are on (PR #101732)
Vyacheslav Levytskyy via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 2 12:32:12 PDT 2024
https://github.com/VyacheslavLevytskyy updated https://github.com/llvm/llvm-project/pull/101732
>From 8f1974faee06eee5cb8707379725c0f285df87ed Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Fri, 2 Aug 2024 11:35:25 -0700
Subject: [PATCH 1/2] scalar virtual registers have proper bit width
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 28 ++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 5 ++-
llvm/test/CodeGen/SPIRV/empty.ll | 5 ++-
llvm/test/CodeGen/SPIRV/transcoding/fadd.ll | 33 +++++++++++++++++--
llvm/test/CodeGen/SPIRV/transcoding/non32.ll | 2 +-
llvm/test/CodeGen/SPIRV/types/or-i1.ll | 2 +-
llvm/test/CodeGen/SPIRV/unnamed-global.ll | 7 ++--
7 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index ed786bd33aa05..262776deaa049 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -76,6 +76,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
SPIRVGlobalRegistry &GR;
MachineRegisterInfo *MRI;
SyncScopeIDs SSIDs;
+ MachineFunction *HasVRegsReset = nullptr;
/// We need to keep track of the number we give to anonymous global values to
/// generate the same name every time when this is needed.
@@ -101,6 +102,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
#undef GET_GLOBALISEL_TEMPORARIES_DECL
private:
+ void resetVRegsType(MachineFunction &MF);
+
// tblgen-erated 'select' implementation, used as the initial selector for
// the patterns that don't require complex C++.
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
@@ -285,12 +288,37 @@ void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB,
InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI);
}
+// To ensure that pattern matching rules are working.
+void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
+ if (HasVRegsReset == &MF)
+ return;
+ HasVRegsReset = &MF;
+
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ LLT Ty = MRI.getType(Reg);
+ if (Ty.isScalar()) {
+ unsigned Bits = Ty.getScalarSizeInBits();
+ switch (Bits) {
+ //case 1:
+ case 32:
+ break;
+ default:
+ MRI.setType(Reg, LLT::scalar(32));
+ }
+ }
+ }
+}
+
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI);
// Defined in SPIRVLegalizerInfo.cpp.
extern bool isTypeFoldingSupported(unsigned Opcode);
bool SPIRVInstructionSelector::select(MachineInstr &I) {
+ resetVRegsType(*I.getParent()->getParent());
+
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 099557a608185..67ef4fb124125 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -315,7 +315,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
SpvType = GR.getSPIRVTypeForVReg(SrcReg);
assert(SpvType && "VReg is expected to have SPIRV type");
LLT SrcLLT = MRI.getType(SrcReg);
- LLT NewT = LLT::scalar(32);
+ LLT NewT;
bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
bool IsVectorFloat =
SpvType->getOpcode() == SPIRV::OpTypeVector &&
@@ -348,6 +348,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
}
} else if (SrcLLT.isVector()) {
+ NewT = LLT::scalar(32); //LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
NewT = LLT::fixed_vector(2, NewT);
if (IsFloat) {
GetIdOp = SPIRV::GET_vfID;
@@ -356,6 +357,8 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
GetIdOp = SPIRV::GET_vID;
DstClass = &SPIRV::vIDRegClass;
}
+ } else {
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
}
Register IdReg = MRI.createGenericVirtualRegister(NewT);
MRI.setRegClass(IdReg, DstClass);
diff --git a/llvm/test/CodeGen/SPIRV/empty.ll b/llvm/test/CodeGen/SPIRV/empty.ll
index 390ab329aea33..29af913a0daee 100644
--- a/llvm/test/CodeGen/SPIRV/empty.ll
+++ b/llvm/test/CodeGen/SPIRV/empty.ll
@@ -1,4 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpCapability Addresses
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
index af76c0e96f9f4..d84fd492a86a8 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
@@ -8,6 +8,13 @@
; CHECK-SPIRV: OpName %[[#r5:]] "r5"
; CHECK-SPIRV: OpName %[[#r6:]] "r6"
; CHECK-SPIRV: OpName %[[#r7:]] "r7"
+; CHECK-SPIRV: OpName %[[#r1d:]] "r1"
+; CHECK-SPIRV: OpName %[[#r2d:]] "r2"
+; CHECK-SPIRV: OpName %[[#r3d:]] "r3"
+; CHECK-SPIRV: OpName %[[#r4d:]] "r4"
+; CHECK-SPIRV: OpName %[[#r5d:]] "r5"
+; CHECK-SPIRV: OpName %[[#r6d:]] "r6"
+; CHECK-SPIRV: OpName %[[#r7d:]] "r7"
; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
@@ -15,7 +22,9 @@
; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
-; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64
+
; CHECK-SPIRV: %[[#r1]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r2]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r3]] = OpFAdd %[[#float]]
@@ -23,8 +32,7 @@
; CHECK-SPIRV: %[[#r5]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r6]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r7]] = OpFAdd %[[#float]]
-
-define spir_kernel void @testFAdd(float %a, float %b) {
+define spir_kernel void @testFAdd_float(float %a, float %b) {
entry:
%r1 = fadd float %a, %b
%r2 = fadd nnan float %a, %b
@@ -35,3 +43,22 @@ entry:
%r7 = fadd nnan ninf float %a, %b
ret void
}
+
+; CHECK-SPIRV: %[[#r1d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r2d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r3d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r4d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r5d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r6d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r7d]] = OpFAdd %[[#double]]
+define spir_kernel void @testFAdd_double(double %a, double %b) {
+entry:
+ %r1 = fadd double %a, %b
+ %r2 = fadd nnan double %a, %b
+ %r3 = fadd ninf double %a, %b
+ %r4 = fadd nsz double %a, %b
+ %r5 = fadd arcp double %a, %b
+ %r6 = fadd fast double %a, %b
+ %r7 = fadd nnan ninf double %a, %b
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
index d44e32141db75..f3f73ce4fee76 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK: OpTypeInt 16
; CHECK: OpIAdd
diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
index 32dc258d85554..3dda3ff8c3c66 100644
--- a/llvm/test/CodeGen/SPIRV/types/or-i1.ll
+++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#BOOL:]] = OpTypeBool
diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
index d2cd4ea8cafc3..f72334bd7752e 100644
--- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll
+++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
@@ -1,5 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0
; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123
>From 467b6df4ae1986164e0dd2620ed59c5a1bffef1e Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Fri, 2 Aug 2024 12:32:00 -0700
Subject: [PATCH 2/2] improve virtual registers of vector type
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 4 +++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 27 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 262776deaa049..6cb68c98ec3aa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -307,6 +307,10 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
default:
MRI.setType(Reg, LLT::scalar(32));
}
+ } else if (!Ty.isPointer()) {
+ if (auto *Def = MRI.getVRegDef(Reg))
+ if (Def->getOpcode() == SPIRV::ASSIGN_TYPE)
+ MRI.setType(Reg, LLT::scalar(32));
}
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 67ef4fb124125..6323fcfbe8051 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -308,6 +308,14 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
MRI.setType(Reg, LLT::scalar(NewSz));
}
+inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
+ bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
+ return IsFloat ? true
+ : SpvType->getOpcode() == SPIRV::OpTypeVector &&
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
+ ->getOpcode() == SPIRV::OpTypeFloat;
+}
+
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -316,12 +324,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
assert(SpvType && "VReg is expected to have SPIRV type");
LLT SrcLLT = MRI.getType(SrcReg);
LLT NewT;
- bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
- bool IsVectorFloat =
- SpvType->getOpcode() == SPIRV::OpTypeVector &&
- GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
- SPIRV::OpTypeFloat;
- IsFloat |= IsVectorFloat;
+ bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
if (SrcLLT.isPointer()) {
@@ -384,8 +387,10 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
- MRI.setRegClass(Reg, &SPIRV::IDRegClass);
+ bool IsFloat = false;//getIsFloat(SpirvTy, *GR);
+ auto RegClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ MRI.setRegClass(NewReg, RegClass);
+ MRI.setRegClass(Reg, RegClass);
}
GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
// This is to make it convenient for Legalizer to get the SPIRVType
@@ -607,8 +612,10 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
- MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
- : LLT::scalar(32));
+ if (IsDstPtr)
+ MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
+// MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
+// : LLT::scalar(32));
}
}
}
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