[llvm] [SPIR-V] Improve test suite pass rate when expensive checks are on (PR #101732)

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``````````bash
git-clang-format --diff 29ef92b9051bca3a35be0cbc5e03d787941f945e 8f1974faee06eee5cb8707379725c0f285df87ed --extensions cpp -- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 262776deaa..af94ee4784 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -301,7 +301,7 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
     if (Ty.isScalar()) {
       unsigned Bits = Ty.getScalarSizeInBits();
       switch (Bits) {
-      //case 1:
+      // case 1:
       case 32:
         break;
       default:
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 67ef4fb124..019b3ee6ee 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -348,7 +348,8 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
       }
     }
   } else if (SrcLLT.isVector()) {
-    NewT = LLT::scalar(32); //LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
+    NewT =
+        LLT::scalar(32); // LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
     NewT = LLT::fixed_vector(2, NewT);
     if (IsFloat) {
       GetIdOp = SPIRV::GET_vfID;

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https://github.com/llvm/llvm-project/pull/101732