[llvm] [NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (PR #98551)

[Artem Belevich via llvm-commits]

================
@@ -106,15 +107,30 @@ enum LoadStore {
   isStoreShift = 6
 };
 
-namespace PTXLdStInstCode {
-enum MemorySemantic {
+// Extends LLVM AtomicOrdering with PTX Orderings:
+using OrderingUnderlyingType = unsigned int;
+enum Ordering : OrderingUnderlyingType {
   NotAtomic = 0, // PTX calls these: "Weak"
-  Volatile = 1,
+  // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed
   Relaxed = 2,
-  Acquire = 3,
-  Release = 4,
-  RelaxedMMIO = 5
+  // Consume = 3,   // Unimplemented in LLVM; NVPTX would map to "Acquire"
+  Acquire = 4,
+  Release = 5,
+  // AcquireRelease = 6, // TODO
+  SequentiallyConsistent = 7,
+  Volatile = 8,
+  RelaxedMMIO = 9,
+  LAST = RelaxedMMIO
 };
+// Values match LLVM AtomicOrdering for common orderings:
+static_assert(Ordering::NotAtomic == (unsigned)AtomicOrdering::NotAtomic);
+static_assert(Ordering::Relaxed == (unsigned)AtomicOrdering::Monotonic);
+static_assert(Ordering::Acquire == (unsigned)AtomicOrdering::Acquire);
+static_assert(Ordering::Release == (unsigned)AtomicOrdering::Release);
+static_assert(Ordering::SequentiallyConsistent ==
+              (unsigned)AtomicOrdering::SequentiallyConsistent);
----------------
Artem-B wrote:

This current version does the job, but it still rubs me the wrong way, a bit. We're explicitly verifying that the values match those of  AtomicOrdering, and *implicitly* relying on the numeric order of enum values by hardcoding them as literals.

I think it would make more sense to explicitly assign enum values to their AtomicOrdering counterparts, and then *explicitly* enforce the ordering via the static_assert. This would better express our intent here.

On the other hand, it's convenient to see the explicit values all in one place, and mixing AtomicOrdering constants and explicit literals would probably look a bit odd, too.

I'll leave it up to you.

https://github.com/llvm/llvm-project/pull/98551