[llvm] MTM: improve operand latency when missing sched info (PR #101389)

[Ramkumar Ramachandra via llvm-commits]

artagnon wrote:

I've updated the CodeGen tests for the RISC-V target as an example to help with the review, and unless I'm mistaken, I do see improvements mixed with changes that have no impact.

https://github.com/llvm/llvm-project/pull/101389