[llvm] [RISCV] Use zext.[b/w/h] instead of th.extu for bitfield extraction (PR #101605)

[via llvm-commits]

joshua-arch1 wrote:

> Is there a xuantie core that supports both zbb and xtheadbb?

Yeah, I have doone some experiments on XuanTie C908 processors, extu rd,rs,15,0 performs worse than zext.h rd,rs and extu rd,rs,31,0 performs worse than zext.w rd,rs.

https://github.com/llvm/llvm-project/pull/101605