[llvm] [RISCV] Generalize existing SRA combine to fix #101040. (PR #101610)

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``````````bash
git-clang-format --diff aca971d336d9c7650120fc0fd6dfe58866408216 08019776fa3423208ee2ab4145039de32a3018df --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2efce6370d..6056e9ce84 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15480,16 +15480,16 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
   if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && N0.hasOneUse()) {
     unsigned ExtSize =
         cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits();
-    if (ShAmt < ExtSize &&
-        N0.getOperand(0).getOpcode() == ISD::SHL && N0.getOperand(0).hasOneUse() &&
+    if (ShAmt < ExtSize && N0.getOperand(0).getOpcode() == ISD::SHL &&
+        N0.getOperand(0).hasOneUse() &&
         isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
       uint64_t LShAmt = N0.getOperand(0).getConstantOperandVal(1);
       if (LShAmt < ExtSize) {
         unsigned Size = VT.getSizeInBits();
         SDLoc ShlDL(N0.getOperand(0));
-        SDValue Shl = DAG.getNode(ISD::SHL, ShlDL, VT,
-                                  N0.getOperand(0).getOperand(0),
-                                  DAG.getConstant(LShAmt + (Size - ExtSize), ShlDL, VT));
+        SDValue Shl =
+            DAG.getNode(ISD::SHL, ShlDL, VT, N0.getOperand(0).getOperand(0),
+                        DAG.getConstant(LShAmt + (Size - ExtSize), ShlDL, VT));
         SDLoc DL(N);
         return DAG.getNode(ISD::SRA, DL, VT, Shl,
                            DAG.getConstant(ShAmt + (Size - ExtSize), DL, VT));

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https://github.com/llvm/llvm-project/pull/101610