[clang] [llvm] [X86][AVX10.2] Support AVX10.2-SATCVT new instructions. (PR #101599)
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Thu Aug 1 18:54:46 PDT 2024
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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You can test this locally with the following command:
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git-clang-format --diff 6867324eeec7c4f297c2f787d9c7b4d751a384c7 707444e10dd9de83e6a195fd8f221b3aeeef19b2 --extensions cpp,inc,h,c -- clang/lib/Headers/avx10_2_512niintrin.h clang/lib/Headers/avx10_2_512satcvtintrin.h clang/lib/Headers/avx10_2niintrin.h clang/lib/Headers/avx10_2satcvtintrin.h clang/test/CodeGen/X86/avx10_2_512ni-builtins.c clang/test/CodeGen/X86/avx10_2_512satcvt-builtins-error.c clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c clang/test/CodeGen/X86/avx10_2ni-builtins.c clang/test/CodeGen/X86/avx10_2satcvt-builtins.c clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Driver/ToolChains/Arch/X86.cpp clang/lib/Headers/immintrin.h clang/lib/Sema/SemaX86.cpp clang/test/CodeGen/attr-target-x86.c clang/test/Driver/x86-target-features.c clang/test/Preprocessor/x86_target_features.c llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.h llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/lib/TargetParser/Host.cpp llvm/lib/TargetParser/X86TargetParser.cpp llvm/test/TableGen/x86-fold-tables.inc llvm/utils/TableGen/X86DisassemblerTables.cpp llvm/utils/TableGen/X86RecognizableInstr.cpp llvm/utils/TableGen/X86RecognizableInstr.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 71cfee8f7c..232c27149b 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -388,48 +388,84 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx_vpermilvar_ps, INTR_TYPE_2OP, X86ISD::VPERMILPV, 0),
X86_INTRINSIC_DATA(avx_vpermilvar_ps_256, INTR_TYPE_2OP, X86ISD::VPERMILPV,
0),
- X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTPH2IBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs256, INTR_TYPE_1OP_MASK, X86ISD::VCVTPH2IBS, X86ISD::VCVTPH2IBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs512, INTR_TYPE_1OP_MASK, X86ISD::VCVTPH2IBS, X86ISD::VCVTPH2IBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTPH2IUBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs256, INTR_TYPE_1OP_MASK, X86ISD::VCVTPH2IUBS, X86ISD::VCVTPH2IUBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs512, INTR_TYPE_1OP_MASK, X86ISD::VCVTPH2IUBS, X86ISD::VCVTPH2IUBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTPS2IBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs256, INTR_TYPE_1OP_MASK, X86ISD::VCVTPS2IBS, X86ISD::VCVTPS2IBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs512, INTR_TYPE_1OP_MASK, X86ISD::VCVTPS2IBS, X86ISD::VCVTPS2IBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTPS2IUBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs256, INTR_TYPE_1OP_MASK, X86ISD::VCVTPS2IUBS, X86ISD::VCVTPS2IUBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs512, INTR_TYPE_1OP_MASK, X86ISD::VCVTPS2IUBS, X86ISD::VCVTPS2IUBS_RND),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTTPH2IBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs256, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPH2IBS, X86ISD::VCVTTPH2IBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs512, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPH2IBS, X86ISD::VCVTTPH2IBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTTPH2IUBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs256, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPH2IUBS, X86ISD::VCVTTPH2IUBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs512, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPH2IUBS, X86ISD::VCVTTPH2IUBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTTPS2IBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs256, INTR_TYPE_1OP_MASK, X86ISD::VCVTTPS2IBS, X86ISD::VCVTTPS2IBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs512, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPS2IBS, X86ISD::VCVTTPS2IBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs128, INTR_TYPE_1OP_MASK, X86ISD::VCVTTPS2IUBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs256, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPS2IUBS, X86ISD::VCVTTPS2IUBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs512, INTR_TYPE_1OP_MASK_SAE, X86ISD::VCVTTPS2IUBS, X86ISD::VCVTTPS2IUBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPH2IBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPH2IBS, X86ISD::VCVTPH2IBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPH2IBS, X86ISD::VCVTPH2IBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPH2IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPH2IUBS, X86ISD::VCVTPH2IUBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPH2IUBS, X86ISD::VCVTPH2IUBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2IBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2IBS, X86ISD::VCVTPS2IBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2IBS, X86ISD::VCVTPS2IBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2IUBS, X86ISD::VCVTPS2IUBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs512, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTPS2IUBS, X86ISD::VCVTPS2IUBS_RND),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTTPH2IBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs256, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPH2IBS, X86ISD::VCVTTPH2IBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs512, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPH2IBS, X86ISD::VCVTTPH2IBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTTPH2IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs256, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPH2IUBS, X86ISD::VCVTTPH2IUBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs512, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPH2IUBS, X86ISD::VCVTTPH2IUBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTTPS2IBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs256, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTTPS2IBS, X86ISD::VCVTTPS2IBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs512, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPS2IBS, X86ISD::VCVTTPS2IBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs128, INTR_TYPE_1OP_MASK,
+ X86ISD::VCVTTPS2IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs256, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPS2IUBS, X86ISD::VCVTTPS2IUBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs512, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::VCVTTPS2IUBS, X86ISD::VCVTTPS2IUBS_SAE),
X86_INTRINSIC_DATA(avx10_vaddpd256, INTR_TYPE_2OP, ISD::FADD,
X86ISD::FADD_RND),
X86_INTRINSIC_DATA(avx10_vaddph256, INTR_TYPE_2OP, ISD::FADD,
X86ISD::FADD_RND),
X86_INTRINSIC_DATA(avx10_vaddps256, INTR_TYPE_2OP, ISD::FADD,
X86ISD::FADD_RND),
- X86_INTRINSIC_DATA(avx10_vcvtnebf162ibs128, INTR_TYPE_1OP, X86ISD::VCVTNEBF162IBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvtnebf162ibs256, INTR_TYPE_1OP, X86ISD::VCVTNEBF162IBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvtnebf162ibs512, INTR_TYPE_1OP, X86ISD::VCVTNEBF162IBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvtnebf162iubs128, INTR_TYPE_1OP, X86ISD::VCVTNEBF162IUBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvtnebf162iubs256, INTR_TYPE_1OP, X86ISD::VCVTNEBF162IUBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvtnebf162iubs512, INTR_TYPE_1OP, X86ISD::VCVTNEBF162IUBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvttnebf162ibs128, INTR_TYPE_1OP, X86ISD::VCVTTNEBF162IBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvttnebf162ibs256, INTR_TYPE_1OP, X86ISD::VCVTTNEBF162IBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvttnebf162ibs512, INTR_TYPE_1OP, X86ISD::VCVTTNEBF162IBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvttnebf162iubs128, INTR_TYPE_1OP, X86ISD::VCVTTNEBF162IUBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvttnebf162iubs256, INTR_TYPE_1OP, X86ISD::VCVTTNEBF162IUBS, 0),
- X86_INTRINSIC_DATA(avx10_vcvttnebf162iubs512, INTR_TYPE_1OP, X86ISD::VCVTTNEBF162IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvtnebf162ibs128, INTR_TYPE_1OP,
+ X86ISD::VCVTNEBF162IBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvtnebf162ibs256, INTR_TYPE_1OP,
+ X86ISD::VCVTNEBF162IBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvtnebf162ibs512, INTR_TYPE_1OP,
+ X86ISD::VCVTNEBF162IBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvtnebf162iubs128, INTR_TYPE_1OP,
+ X86ISD::VCVTNEBF162IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvtnebf162iubs256, INTR_TYPE_1OP,
+ X86ISD::VCVTNEBF162IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvtnebf162iubs512, INTR_TYPE_1OP,
+ X86ISD::VCVTNEBF162IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvttnebf162ibs128, INTR_TYPE_1OP,
+ X86ISD::VCVTTNEBF162IBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvttnebf162ibs256, INTR_TYPE_1OP,
+ X86ISD::VCVTTNEBF162IBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvttnebf162ibs512, INTR_TYPE_1OP,
+ X86ISD::VCVTTNEBF162IBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvttnebf162iubs128, INTR_TYPE_1OP,
+ X86ISD::VCVTTNEBF162IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvttnebf162iubs256, INTR_TYPE_1OP,
+ X86ISD::VCVTTNEBF162IUBS, 0),
+ X86_INTRINSIC_DATA(avx10_vcvttnebf162iubs512, INTR_TYPE_1OP,
+ X86ISD::VCVTTNEBF162IUBS, 0),
X86_INTRINSIC_DATA(avx10_vmpsadbw_512, INTR_TYPE_3OP_IMM8, X86ISD::MPSADBW,
0),
X86_INTRINSIC_DATA(avx2_mpsadbw, INTR_TYPE_3OP_IMM8, X86ISD::MPSADBW, 0),
``````````
</details>
https://github.com/llvm/llvm-project/pull/101599
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