[llvm] [InstCombine] Canonicalize more saturated-add variants (PR #100008)
Rose Silicon via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 1 13:55:49 PDT 2024
https://github.com/RSilicon updated https://github.com/llvm/llvm-project/pull/100008
>From 3fcb38daff039bfaf0bcae1901d2f909b39b14b4 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sun, 7 Jul 2024 17:51:02 -0400
Subject: [PATCH 1/3] Pre-commit tests (NFC)
---
.../InstCombine/saturating-add-sub.ll | 436 ++++++++++++++++++
1 file changed, 436 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
index bf1568f1cd8c0..722659ae2a836 100644
--- a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
+++ b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
@@ -1395,6 +1395,442 @@ define i32 @uadd_sat(i32 %x, i32 %y) {
%r = select i1 %c, i32 -1, i32 %a
ret i32 %r
}
+
+define i32 @uadd_sat_flipped(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -11
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -11
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped2(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -10
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -10
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped3(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped3(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -8
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -8
+ %add = add nuw i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative Test
+
+define i32 @uadd_sat_flipped3_neg_no_nuw(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped3_neg_no_nuw(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -8
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -8
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped4(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped4(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -10
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp uge i32 %x, -9
+ %add = add nuw i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+; Negative Test
+
+define i32 @uadd_sat_flipped4_neg_no_nuw(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped4_neg_no_nuw(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -10
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp uge i32 %x, -9
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped5(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped5(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp uge i32 %x, -8
+ %add = add nuw i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative test
+
+define i32 @uadd_sat_flipped5_neg_no_nuw(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped5_neg_no_nuw(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp uge i32 %x, -8
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped6(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped6(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -9
+ %add = add nuw i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_negative_one(i32 %x) {
+; CHECK-LABEL: @uadd_sat_negative_one(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], -1
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp eq i32 %x, -1
+ %add = add i32 %x, 1
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_negative_one_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_negative_one_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp eq i32 %x, poison
+ %add = add i32 %x, 1
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_negative_one_poison_cmp(i32 %x) {
+; CHECK-LABEL: @uadd_sat_negative_one_poison_cmp(
+; CHECK-NEXT: ret i32 -1
+;
+ %cmp = icmp eq i32 %x, -1
+ %add = add i32 %x, poison
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_negative_one_poison_all(i32 %x) {
+; CHECK-LABEL: @uadd_sat_negative_one_poison_all(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp eq i32 %x, poison
+ %add = add i32 %x, poison
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative test
+
+define i32 @uadd_sat_flipped_neg_no_nuw(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_neg_no_nuw(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -9
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_poison(i32 %x, i32 %y) {
+; CHECK-LABEL: @uadd_sat_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %notx = xor i32 %x, -1
+ %a = add i32 %y, %x
+ %c = icmp ult i32 %notx, poison
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define i32 @uadd_sat_flipped_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp ugt i32 %x, poison
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped2_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped2_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp ugt i32 %x, poison
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped3_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped3_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp ult i32 %x, poison
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_flipped4_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped4_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp ult i32 %x, poison
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_add_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_add_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp ult i32 %x, poison
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+define i32 @uadd_sat_add_compare_poison(i32 %x) {
+; CHECK-LABEL: @uadd_sat_add_compare_poison(
+; CHECK-NEXT: ret i32 poison
+;
+ %cmp = icmp ult i32 %x, poison
+ %add = add i32 %x, poison
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+define <2 x i8> @uadd_sat_flipped4_vector(<2 x i8> %x) {
+; CHECK-LABEL: @uadd_sat_flipped4_vector(
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> <i8 9, i8 9>)
+; CHECK-NEXT: ret <2 x i8> [[COND]]
+;
+ %cmp = icmp ult <2 x i8> %x, <i8 -10, i8 -10>
+ %add = add <2 x i8> %x, <i8 9, i8 9>
+ %cond = select <2 x i1> %cmp, <2 x i8> %add, <2 x i8> <i8 -1, i8 -1>
+ ret <2 x i8> %cond
+}
+
+define <2 x i8> @uadd_sat_flipped4_poison_vector(<2 x i8> %x) {
+; CHECK-LABEL: @uadd_sat_flipped4_poison_vector(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 -10, i8 poison>
+; CHECK-NEXT: [[ADD:%.*]] = add <2 x i8> [[X]], <i8 9, i8 9>
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[ADD]], <2 x i8> <i8 -1, i8 -1>
+; CHECK-NEXT: ret <2 x i8> [[COND]]
+;
+ %cmp = icmp ult <2 x i8> %x, <i8 -10, i8 poison>
+ %add = add <2 x i8> %x, <i8 9, i8 9>
+ %cond = select <2 x i1> %cmp, <2 x i8> %add,<2 x i8> <i8 -1, i8 -1>
+ ret <2 x i8> %cond
+}
+
+define <2 x i8> @uadd_sat_flipped4_poison_vector_compare(<2 x i8> %x) {
+; CHECK-LABEL: @uadd_sat_flipped4_poison_vector_compare(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 -10, i8 poison>
+; CHECK-NEXT: [[ADD:%.*]] = add <2 x i8> [[X]], <i8 9, i8 poison>
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[ADD]], <2 x i8> <i8 -1, i8 -1>
+; CHECK-NEXT: ret <2 x i8> [[COND]]
+;
+ %cmp = icmp ult <2 x i8> %x, <i8 -10, i8 poison>
+ %add = add <2 x i8> %x, <i8 9, i8 poison>
+ %cond = select <2 x i1> %cmp, <2 x i8> %add,<2 x i8> <i8 -1, i8 -1>
+ ret <2 x i8> %cond
+}
+
+define <2 x i8> @uadd_sat_flipped4_poison_vector_compare2(<2 x i8> %x) {
+; CHECK-LABEL: @uadd_sat_flipped4_poison_vector_compare2(
+; CHECK-NEXT: ret <2 x i8> <i8 -1, i8 -1>
+;
+ %cmp = icmp ult <2 x i8> %x, <i8 -10, i8 poison>
+ %add = add <2 x i8> %x, <i8 poison, i8 poison>
+ %cond = select <2 x i1> %cmp, <2 x i8> %add,<2 x i8> <i8 -1, i8 -1>
+ ret <2 x i8> %cond
+}
+
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_too_big(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_too_big(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -8
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ult i32 %x, -8
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -13
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp uge i32 %x, -12
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds2(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -12
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -12
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds3(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds3(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -12
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, -12
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds4(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds4(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp uge i32 %x, -8
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 -1, i32 %add
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds5(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds5(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -8
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ult i32 %x, -8
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds6(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds6(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -11
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ule i32 %x, -12
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds7(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds7(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -11
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ule i32 %x, -12
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
+; Negative test:
+
+define i32 @uadd_sat_flipped_wrong_bounds8(i32 %x) {
+; CHECK-LABEL: @uadd_sat_flipped_wrong_bounds8(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -12
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ult i32 %x, -12
+ %add = add i32 %x, 9
+ %cond = select i1 %cmp, i32 %add, i32 -1
+ ret i32 %cond
+}
+
define i32 @uadd_sat_nonstrict(i32 %x, i32 %y) {
; CHECK-LABEL: @uadd_sat_nonstrict(
; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
>From 343e2380652adc8218554100a8d0d87bbe4d9a2a Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 30 Jul 2024 12:55:39 -0400
Subject: [PATCH 2/3] [InstCombine] Canonicalize more saturated-add variants
LLVM is not evaluating X u > C, a, b the same way it evaluates X <= C, b, a.
To fix this, let's move the folds to after the canonicalization of -1 to TrueVal.
Let's allow splat vectors with poison elements to be recognized too!
Finally, for completion, handle the one case that isn't caught by the above checks because it is canonicalized to eq:
X == -1 ? -1 : X + 1 -> uadd.sat(X, 1)
Alive2 Proof:
https://alive2.llvm.org/ce/z/WEcgYH
---
.../InstCombine/InstCombineSelect.cpp | 49 ++++++--
.../InstCombine/saturating-add-sub.ll | 116 ++----------------
2 files changed, 49 insertions(+), 116 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index a22ee1de0ac21..673596573582c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -977,14 +977,7 @@ static Value *canonicalizeSaturatedAdd(ICmpInst *Cmp, Value *TVal, Value *FVal,
Value *Cmp1 = Cmp->getOperand(1);
ICmpInst::Predicate Pred = Cmp->getPredicate();
Value *X;
- const APInt *C, *CmpC;
- if (Pred == ICmpInst::ICMP_ULT &&
- match(TVal, m_Add(m_Value(X), m_APInt(C))) && X == Cmp0 &&
- match(FVal, m_AllOnes()) && match(Cmp1, m_APInt(CmpC)) && *CmpC == ~*C) {
- // (X u< ~C) ? (X + C) : -1 --> uadd.sat(X, C)
- return Builder.CreateBinaryIntrinsic(
- Intrinsic::uadd_sat, X, ConstantInt::get(X->getType(), *C));
- }
+ const APInt *C;
// Match unsigned saturated add of 2 variables with an unnecessary 'not'.
// There are 8 commuted variants.
@@ -996,6 +989,46 @@ static Value *canonicalizeSaturatedAdd(ICmpInst *Cmp, Value *TVal, Value *FVal,
if (!match(TVal, m_AllOnes()))
return nullptr;
+ // uge -1 is canonicalized to eq -1 and requires special handling
+ // (a == -1) ? -1 : a + 1 -> uadd.sat(a, 1)
+ if (Pred == ICmpInst::ICMP_EQ) {
+ if (match(FVal, m_Add(m_Specific(Cmp0), m_One())) &&
+ match(Cmp1, m_AllOnes())) {
+ return Builder.CreateBinaryIntrinsic(
+ Intrinsic::uadd_sat, Cmp0, ConstantInt::get(Cmp0->getType(), 1));
+ }
+ return nullptr;
+ }
+
+ if ((Pred == ICmpInst::ICMP_UGE || Pred == ICmpInst::ICMP_UGT) &&
+ match(FVal, m_Add(m_Specific(Cmp0), m_APIntAllowPoison(C))) &&
+ match(Cmp1, m_SpecificIntAllowPoison(~*C))) {
+ // (X u> ~C) ? -1 : (X + C) --> uadd.sat(X, C)
+ // (X u>= ~C)? -1 : (X + C) --> uadd.sat(X, C)
+ return Builder.CreateBinaryIntrinsic(Intrinsic::uadd_sat, Cmp0,
+ ConstantInt::get(Cmp0->getType(), *C));
+ }
+
+ // Negative one does not work here because X u> -1 ? -1, X + -1 is not a
+ // saturated add.
+ if (Pred == ICmpInst::ICMP_UGT &&
+ match(FVal, m_Add(m_Specific(Cmp0), m_APIntAllowPoison(C))) &&
+ match(Cmp1, m_SpecificIntAllowPoison(~*C - 1)) && !C->isAllOnes()) {
+ // (X u> ~C - 1) ? -1 : (X + C) --> uadd.sat(X, C)
+ return Builder.CreateBinaryIntrinsic(Intrinsic::uadd_sat, Cmp0,
+ ConstantInt::get(Cmp0->getType(), *C));
+ }
+
+ // Zero does not work here because X u>= 0 ? -1 : X -> is always -1, which is
+ // not a saturated add.
+ if (Pred == ICmpInst::ICMP_UGE &&
+ match(FVal, m_Add(m_Specific(Cmp0), m_APIntAllowPoison(C))) &&
+ match(Cmp1, m_SpecificIntAllowPoison(-*C)) && !C->isZero()) {
+ // (X u >= -C) ? -1 : (X + C) --> uadd.sat(X, C)
+ return Builder.CreateBinaryIntrinsic(Intrinsic::uadd_sat, Cmp0,
+ ConstantInt::get(Cmp0->getType(), *C));
+ }
+
// Canonicalize predicate to less-than or less-or-equal-than.
if (Pred == ICmpInst::ICMP_UGT || Pred == ICmpInst::ICMP_UGE) {
std::swap(Cmp0, Cmp1);
diff --git a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
index 722659ae2a836..c8cecceb261fb 100644
--- a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
+++ b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
@@ -1398,9 +1398,7 @@ define i32 @uadd_sat(i32 %x, i32 %y) {
define i32 @uadd_sat_flipped(i32 %x) {
; CHECK-LABEL: @uadd_sat_flipped(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -11
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 9)
; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp ugt i32 %x, -11
@@ -1411,9 +1409,7 @@ define i32 @uadd_sat_flipped(i32 %x) {
define i32 @uadd_sat_flipped2(i32 %x) {
; CHECK-LABEL: @uadd_sat_flipped2(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -10
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 9)
; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp ugt i32 %x, -10
@@ -1450,80 +1446,9 @@ define i32 @uadd_sat_flipped3_neg_no_nuw(i32 %x) {
ret i32 %cond
}
-define i32 @uadd_sat_flipped4(i32 %x) {
-; CHECK-LABEL: @uadd_sat_flipped4(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -10
-; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
-; CHECK-NEXT: ret i32 [[COND]]
-;
- %cmp = icmp uge i32 %x, -9
- %add = add nuw i32 %x, 9
- %cond = select i1 %cmp, i32 %add, i32 -1
- ret i32 %cond
-}
-
-; Negative Test
-
-define i32 @uadd_sat_flipped4_neg_no_nuw(i32 %x) {
-; CHECK-LABEL: @uadd_sat_flipped4_neg_no_nuw(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -10
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -1
-; CHECK-NEXT: ret i32 [[COND]]
-;
- %cmp = icmp uge i32 %x, -9
- %add = add i32 %x, 9
- %cond = select i1 %cmp, i32 %add, i32 -1
- ret i32 %cond
-}
-
-define i32 @uadd_sat_flipped5(i32 %x) {
-; CHECK-LABEL: @uadd_sat_flipped5(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
-; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
-; CHECK-NEXT: ret i32 [[COND]]
-;
- %cmp = icmp uge i32 %x, -8
- %add = add nuw i32 %x, 9
- %cond = select i1 %cmp, i32 -1, i32 %add
- ret i32 %cond
-}
-
-; Negative test
-
-define i32 @uadd_sat_flipped5_neg_no_nuw(i32 %x) {
-; CHECK-LABEL: @uadd_sat_flipped5_neg_no_nuw(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
-; CHECK-NEXT: ret i32 [[COND]]
-;
- %cmp = icmp uge i32 %x, -8
- %add = add i32 %x, 9
- %cond = select i1 %cmp, i32 -1, i32 %add
- ret i32 %cond
-}
-
-define i32 @uadd_sat_flipped6(i32 %x) {
-; CHECK-LABEL: @uadd_sat_flipped6(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
-; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
-; CHECK-NEXT: ret i32 [[COND]]
-;
- %cmp = icmp ugt i32 %x, -9
- %add = add nuw i32 %x, 9
- %cond = select i1 %cmp, i32 -1, i32 %add
- ret i32 %cond
-}
-
define i32 @uadd_sat_negative_one(i32 %x) {
; CHECK-LABEL: @uadd_sat_negative_one(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], -1
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 1
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 1)
; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp eq i32 %x, -1
@@ -1562,21 +1487,6 @@ define i32 @uadd_sat_negative_one_poison_all(i32 %x) {
ret i32 %cond
}
-; Negative test
-
-define i32 @uadd_sat_flipped_neg_no_nuw(i32 %x) {
-; CHECK-LABEL: @uadd_sat_flipped_neg_no_nuw(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -9
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X]], 9
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 -1, i32 [[ADD]]
-; CHECK-NEXT: ret i32 [[COND]]
-;
- %cmp = icmp ugt i32 %x, -9
- %add = add i32 %x, 9
- %cond = select i1 %cmp, i32 -1, i32 %add
- ret i32 %cond
-}
-
define i32 @uadd_sat_poison(i32 %x, i32 %y) {
; CHECK-LABEL: @uadd_sat_poison(
; CHECK-NEXT: ret i32 poison
@@ -1661,9 +1571,7 @@ define <2 x i8> @uadd_sat_flipped4_vector(<2 x i8> %x) {
define <2 x i8> @uadd_sat_flipped4_poison_vector(<2 x i8> %x) {
; CHECK-LABEL: @uadd_sat_flipped4_poison_vector(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 -10, i8 poison>
-; CHECK-NEXT: [[ADD:%.*]] = add <2 x i8> [[X]], <i8 9, i8 9>
-; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[ADD]], <2 x i8> <i8 -1, i8 -1>
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> <i8 9, i8 9>)
; CHECK-NEXT: ret <2 x i8> [[COND]]
;
%cmp = icmp ult <2 x i8> %x, <i8 -10, i8 poison>
@@ -1674,9 +1582,7 @@ define <2 x i8> @uadd_sat_flipped4_poison_vector(<2 x i8> %x) {
define <2 x i8> @uadd_sat_flipped4_poison_vector_compare(<2 x i8> %x) {
; CHECK-LABEL: @uadd_sat_flipped4_poison_vector_compare(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 -10, i8 poison>
-; CHECK-NEXT: [[ADD:%.*]] = add <2 x i8> [[X]], <i8 9, i8 poison>
-; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[ADD]], <2 x i8> <i8 -1, i8 -1>
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> <i8 9, i8 9>)
; CHECK-NEXT: ret <2 x i8> [[COND]]
;
%cmp = icmp ult <2 x i8> %x, <i8 -10, i8 poison>
@@ -2172,9 +2078,7 @@ define i32 @uadd_sat_not_commute_select_uge_commute_add(i32 %x, i32 %y) {
define i32 @uadd_sat_constant(i32 %x) {
; CHECK-LABEL: @uadd_sat_constant(
-; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], 42
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], -43
-; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 -1, i32 [[A]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 42)
; CHECK-NEXT: ret i32 [[R]]
;
%a = add i32 %x, 42
@@ -2240,9 +2144,7 @@ define i32 @uadd_sat_canon_y_nuw(i32 %x, i32 %y) {
define <4 x i32> @uadd_sat_constant_vec(<4 x i32> %x) {
; CHECK-LABEL: @uadd_sat_constant_vec(
-; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 42, i32 42, i32 42>
-; CHECK-NEXT: [[C:%.*]] = icmp ugt <4 x i32> [[X]], <i32 -43, i32 -43, i32 -43, i32 -43>
-; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[A]]
+; CHECK-NEXT: [[R:%.*]] = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> [[X:%.*]], <4 x i32> <i32 42, i32 42, i32 42, i32 42>)
; CHECK-NEXT: ret <4 x i32> [[R]]
;
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
@@ -2264,9 +2166,7 @@ define <4 x i32> @uadd_sat_constant_vec_commute(<4 x i32> %x) {
define <4 x i32> @uadd_sat_constant_vec_commute_undefs(<4 x i32> %x) {
; CHECK-LABEL: @uadd_sat_constant_vec_commute_undefs(
-; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 42, i32 42, i32 poison>
-; CHECK-NEXT: [[C:%.*]] = icmp ult <4 x i32> [[X]], <i32 -43, i32 -43, i32 poison, i32 -43>
-; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i32> [[A]], <4 x i32> <i32 -1, i32 poison, i32 -1, i32 -1>
+; CHECK-NEXT: [[R:%.*]] = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> [[X:%.*]], <4 x i32> <i32 42, i32 42, i32 42, i32 42>)
; CHECK-NEXT: ret <4 x i32> [[R]]
;
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 poison>
>From b2b53df057a4b0cd2e998d86458c0c4abf85e298 Mon Sep 17 00:00:00 2001
From: Rose Silicon <gfunni234 at gmail.com>
Date: Thu, 1 Aug 2024 16:55:40 -0400
Subject: [PATCH 3/3] Update saturating-add-sub.ll
---
llvm/test/Transforms/InstCombine/saturating-add-sub.ll | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
index c8cecceb261fb..15776e1977572 100644
--- a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
+++ b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll
@@ -1457,16 +1457,6 @@ define i32 @uadd_sat_negative_one(i32 %x) {
ret i32 %cond
}
-define i32 @uadd_sat_negative_one_poison(i32 %x) {
-; CHECK-LABEL: @uadd_sat_negative_one_poison(
-; CHECK-NEXT: ret i32 poison
-;
- %cmp = icmp eq i32 %x, poison
- %add = add i32 %x, 1
- %cond = select i1 %cmp, i32 -1, i32 %add
- ret i32 %cond
-}
-
define i32 @uadd_sat_negative_one_poison_cmp(i32 %x) {
; CHECK-LABEL: @uadd_sat_negative_one_poison_cmp(
; CHECK-NEXT: ret i32 -1
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