[llvm] [NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (PR #98551)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 40940980bf87832b0275dcfa91ab03738c569b18 e865fc3f5c0c51d60dfd1f74bf47ba72374e7c0f --extensions h,cpp -- llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp llvm/lib/Target/NVPTX/NVPTX.h llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h llvm/lib/Target/NVPTX/NVPTXUtilities.h
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
index 1b9bf1e061..939cb2afe0 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -127,7 +127,8 @@ static_assert(Ordering::NotAtomic == (unsigned)AtomicOrdering::NotAtomic);
 static_assert(Ordering::Relaxed == (unsigned)AtomicOrdering::Monotonic);
 static_assert(Ordering::Acquire == (unsigned)AtomicOrdering::Acquire);
 static_assert(Ordering::Release == (unsigned)AtomicOrdering::Release);
-static_assert(Ordering::SequentiallyConsistent == (unsigned)AtomicOrdering::SequentiallyConsistent);        
+static_assert(Ordering::SequentiallyConsistent ==
+              (unsigned)AtomicOrdering::SequentiallyConsistent);
 
 namespace PTXLdStInstCode {
 enum AddressSpace {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index d2dc37fc2a..25c198f012 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -978,8 +978,9 @@ NVPTX::Ordering NVPTXDAGToDAGISel::insertMemoryInstructionFence(SDLoc DL,
     break;
   }
   default:
-    report_fatal_error(formatv("Unexpected fence ordering: \"{}\".",
-                               OrderingToCString(NVPTX::Ordering(FenceOrdering))));
+    report_fatal_error(
+        formatv("Unexpected fence ordering: \"{}\".",
+                OrderingToCString(NVPTX::Ordering(FenceOrdering))));
   }
 
   return InstructionOrdering;
@@ -2026,7 +2027,8 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
     break;
   case NVPTXISD::StoreV4:
     VecType = NVPTX::PTXLdStInstCode::V4;
-    Ops.append({N->getOperand(1), N->getOperand(2), N->getOperand(3), N->getOperand(4)});
+    Ops.append({N->getOperand(1), N->getOperand(2), N->getOperand(3),
+                N->getOperand(4)});
     N2 = N->getOperand(5);
     break;
   default:
@@ -2043,12 +2045,9 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
     ToTypeWidth = 32;
   }
 
-  Ops.append({
-      getI32Imm(InstructionOrdering, DL),
-      getI32Imm(CodeAddrSpace, DL),
-      getI32Imm(VecType, DL),
-      getI32Imm(ToType, DL),
-      getI32Imm(ToTypeWidth, DL)});
+  Ops.append({getI32Imm(InstructionOrdering, DL), getI32Imm(CodeAddrSpace, DL),
+              getI32Imm(VecType, DL), getI32Imm(ToType, DL),
+              getI32Imm(ToTypeWidth, DL)});
 
   if (SelectDirectAddr(N2, Addr)) {
     switch (N->getOpcode()) {
@@ -2461,9 +2460,7 @@ bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) {
   for (unsigned i = 0; i < NumElts; ++i)
     Ops.push_back(N->getOperand(i + 3));
   Ops.append({CurDAG->getTargetConstant(ParamVal, DL, MVT::i32),
-      CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32),
-      Chain,
-      Glue});
+              CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32), Chain, Glue});
 
   // Determine target opcode
   // If we have an i1, use an 8-bit store. The lowering code in

``````````

</details>


https://github.com/llvm/llvm-project/pull/98551