[llvm] [AArch64] Peephole optimization to remove redundant csel instructions (PR #101483)

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git-clang-format --diff 2d3655037ccfa276cb0949c2ce0cff56985f6637 a8a7246127d9b3a2004a37c210c1218d5c1cbc16 --extensions cpp -- llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
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diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 5c5a9df82d..b65401ef93 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -52,14 +52,15 @@
 //   %1:fpr64 = nofpexcept FCVTNv4i16 %0:fpr128, implicit $fpcr
 //   %2:fpr64 = MOVID 0
 //   %4:fpr128 = IMPLICIT_DEF
-//   %3:fpr128 = INSERT_SUBREG %4:fpr128(tied-def 0), killed %2:fpr64, %subreg.dsub
-//   %6:fpr128 = IMPLICIT_DEF
-//   %5:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub
-//   %7:fpr128 = INSvi64lane %5:fpr128(tied-def 0), 1, killed %3:fpr128, 0
+//   %3:fpr128 = INSERT_SUBREG %4:fpr128(tied-def 0), killed %2:fpr64,
+//   %subreg.dsub %6:fpr128 = IMPLICIT_DEF %5:fpr128 = INSERT_SUBREG
+//   %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub %7:fpr128 =
+//   INSvi64lane %5:fpr128(tied-def 0), 1, killed %3:fpr128, 0
 //   ==>
 //   %1:fpr64 = nofpexcept FCVTNv4i16 %0:fpr128, implicit $fpcr
 //   %6:fpr128 = IMPLICIT_DEF
-//   %7:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub
+//   %7:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64,
+//   %subreg.dsub
 //
 // 8. Remove redundant CSELs that select between identical registers, by
 //    replacing them with unconditional moves.

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https://github.com/llvm/llvm-project/pull/101483