[llvm] [InstCombine] Handle ceil division idiom (PR #100977)

[Nikita Popov via llvm-commits]

nikic wrote:

@dtcxzyw The motivation for this were the regressions we saw from https://github.com/llvm/llvm-project/pull/95556. I think most divideCeil() uses have a constant power of two RHS though, so they will produce a lshr pattern, not the udiv one handled here.

But it's possible that we don't actually know that the addition won't overflow in the hot cases. The key one is probably this in DataLayout:
```
  TypeSize getTypeStoreSize(Type *Ty) const {
    TypeSize BaseSize = getTypeSizeInBits(Ty);
    return {divideCeil(BaseSize.getKnownMinValue(), 8), BaseSize.isScalable()};
  }
```
This works on uint64_t and nothing tells us that it will not overflow :(


https://github.com/llvm/llvm-project/pull/100977