[compiler-rt] [RISCV][compiler-rt] create __riscv__cpu_model for vendorID, ArchID, … (PR #101449)

[Piyou Chen via llvm-commits]

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/101449

>From fc861054373c786d4588bb3072d566b6f6940cb8 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 31 Jul 2024 20:22:01 -0700
Subject: [PATCH 1/2] [RISCV][compiler-rt] create __riscv__cpu_model for
 vendorID, ArchID, ImplID

---
 compiler-rt/lib/builtins/cpu_model/riscv.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 92931fae64fbf..d643ddefd334d 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -16,11 +16,16 @@ struct {
 
 #define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
 struct {
-  unsigned vendorID;
   unsigned length;
   unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
 } __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
 
+struct {
+  unsigned mVendorID;
+  unsigned mArchID;
+  unsigned mImplID;
+} __riscv__cpu_model __attribute__((visibility("hidden"), nocommon));
+
 // NOTE: Should sync-up with RISCVFeatures.td
 // TODO: Maybe generate a header from tablegen then include it.
 #define A_GROUPID 0
@@ -208,8 +213,10 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
   // will be cleared to -1, and its value set to 0.
   // This unsets all extension bitmask bits.
 
-  // Init vendor extension
-  __riscv_vendor_feature_bits.vendorID = Hwprobes[2].value;
+  // Init VendorID, ArchID, ImplID
+  __riscv__cpu_model.mVendorID = Hwprobes[2].value;
+  __riscv__cpu_model.mArchID = Hwprobes[3].value;
+  __riscv__cpu_model.mImplID = Hwprobes[4].value;
 
   // Init standard extension
   // TODO: Maybe Extension implied generate from tablegen?
@@ -297,9 +304,9 @@ void CONSTRUCTOR_ATTRIBUTE __init_riscv_feature_bits() {
 
 #if defined(__linux__)
   struct riscv_hwprobe Hwprobes[] = {
-      {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0},
-      {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
-      {RISCV_HWPROBE_KEY_MVENDORID, 0},
+      {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0}, {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
+      {RISCV_HWPROBE_KEY_MVENDORID, 0},     {RISCV_HWPROBE_KEY_MARCHID, 0},
+      {RISCV_HWPROBE_KEY_MIMPID, 0},
   };
   if (initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0])))
     return;

>From 1289c26fdc840479d1fbdcbbfa793c79cc1233fd Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 1 Aug 2024 02:40:19 -0700
Subject: [PATCH 2/2] __riscv__cpu_model -> __riscv_cpu_model

---
 compiler-rt/lib/builtins/cpu_model/riscv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index d643ddefd334d..55e594588f94f 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -24,7 +24,7 @@ struct {
   unsigned mVendorID;
   unsigned mArchID;
   unsigned mImplID;
-} __riscv__cpu_model __attribute__((visibility("hidden"), nocommon));
+} __riscv_cpu_model __attribute__((visibility("hidden"), nocommon));
 
 // NOTE: Should sync-up with RISCVFeatures.td
 // TODO: Maybe generate a header from tablegen then include it.
@@ -214,9 +214,9 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
   // This unsets all extension bitmask bits.
 
   // Init VendorID, ArchID, ImplID
-  __riscv__cpu_model.mVendorID = Hwprobes[2].value;
-  __riscv__cpu_model.mArchID = Hwprobes[3].value;
-  __riscv__cpu_model.mImplID = Hwprobes[4].value;
+  __riscv_cpu_model.mVendorID = Hwprobes[2].value;
+  __riscv_cpu_model.mArchID = Hwprobes[3].value;
+  __riscv_cpu_model.mImplID = Hwprobes[4].value;
 
   // Init standard extension
   // TODO: Maybe Extension implied generate from tablegen?