[llvm] 129a8e1 - [AArch64] Add tests for redundant csel instructions. NFC (#101014)

[via llvm-commits]

Author: Marina
Date: 2024-08-01T07:08:07+01:00
New Revision: 129a8e1b756aa4e5932169ed2f1f7dbad692f44d

URL: https://github.com/llvm/llvm-project/commit/129a8e1b756aa4e5932169ed2f1f7dbad692f44d
DIFF: https://github.com/llvm/llvm-project/commit/129a8e1b756aa4e5932169ed2f1f7dbad692f44d.diff

LOG: [AArch64] Add tests for redundant csel instructions. NFC (#101014)

Added: 
    llvm/test/CodeGen/AArch64/peephole-csel.ll
    llvm/test/CodeGen/AArch64/peephole-csel.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/peephole-csel.ll b/llvm/test/CodeGen/AArch64/peephole-csel.ll
new file mode 100644
index 0000000000000..3f92943b11eb1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/peephole-csel.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+define void @peephole_csel(ptr %dst, i1 %0, i1 %cmp) {
+; CHECK-LABEL: peephole_csel:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    tst w2, #0x1
+; CHECK-NEXT:    mov w8, #1 // =0x1
+; CHECK-NEXT:    csel x9, xzr, xzr, eq
+; CHECK-NEXT:    tst w1, #0x1
+; CHECK-NEXT:    csel x8, x8, x9, eq
+; CHECK-NEXT:    str x8, [x0]
+; CHECK-NEXT:    ret
+entry:
+  br i1 %0, label %then, label %exit
+
+then:                                             ; preds = %entry
+  ; The donothing() is needed to make make this block less interesting to
+  ; SimplifyCFG. Otherwise we may not get the csel that we want to test.
+  call void @llvm.donothing()
+  br i1 %cmp, label %true, label %exit
+
+true:                                             ; preds = %then
+  ; Same as above
+  call void @llvm.donothing()
+  br label %exit
+
+exit: ; preds = %true, %then, %entry
+  %x = phi i64 [ 0, %true ], [ 0, %then ], [ 1, %entry ]
+  store i64 %x, ptr %dst, align 8
+  ret void
+}

diff  --git a/llvm/test/CodeGen/AArch64/peephole-csel.mir b/llvm/test/CodeGen/AArch64/peephole-csel.mir
new file mode 100644
index 0000000000000..5077441a33788
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/peephole-csel.mir
@@ -0,0 +1,112 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -run-pass=aarch64-mi-peephole-opt -verify-machineinstrs | FileCheck %s
+
+---
+name:            peephole_cselxr_same
+registers:
+  - { id: 1, class: gpr64, preferred-register: '' }
+  - { id: 2, class: gpr64, preferred-register: '' }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; CHECK-LABEL: name: peephole_cselxr_same
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY1]], [[COPY1]], 0, implicit $nzcv
+    ; CHECK-NEXT: RET_ReallyLR
+    %3:gpr64 = COPY $x1
+    %4:gpr64 = COPY $x0
+    $xzr = ANDSXri %3, 0, implicit-def $nzcv
+    %5:gpr64 = CSELXr %4, %4, 0, implicit $nzcv
+    RET_ReallyLR
+
+...
+---
+name:            peephole_cselwr_same
+registers:
+  - { id: 1, class: gpr32, preferred-register: '' }
+  - { id: 2, class: gpr32, preferred-register: '' }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: peephole_cselwr_same
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[COPY1]], 0, implicit $nzcv
+    ; CHECK-NEXT: RET_ReallyLR
+    %3:gpr32 = COPY $w1
+    %4:gpr32 = COPY $w0
+    $wzr = ANDSWri %3, 0, implicit-def $nzcv
+    %5:gpr32 = CSELWr %4, %4, 0, implicit $nzcv
+    RET_ReallyLR
+
+...
+---
+name:            peephole_cselxr_
diff erent
+registers:
+  - { id: 1, class: gpr64, preferred-register: '' }
+  - { id: 2, class: gpr64, preferred-register: '' }
+liveins:
+  - { reg: '$x0', virtual-reg: '%1' }
+  - { reg: '$x1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; CHECK-LABEL: name: peephole_cselxr_
diff erent
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY]], [[COPY1]], 0, implicit $nzcv
+    ; CHECK-NEXT: RET_ReallyLR
+    %3:gpr64 = COPY $x1
+    %4:gpr64 = COPY $x0
+    $xzr = ANDSXri %3, 0, implicit-def $nzcv
+    %5:gpr64 = CSELXr %3, %4, 0, implicit $nzcv
+    RET_ReallyLR
+
+...
+---
+name:            peephole_cselwr_
diff erent
+registers:
+  - { id: 1, class: gpr32, preferred-register: '' }
+  - { id: 2, class: gpr32, preferred-register: '' }
+liveins:
+  - { reg: '$w0', virtual-reg: '%1' }
+  - { reg: '$w1', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: peephole_cselwr_
diff erent
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[COPY1]], 0, implicit $nzcv
+    ; CHECK-NEXT: RET_ReallyLR
+    %3:gpr32 = COPY $w1
+    %4:gpr32 = COPY $w0
+    $wzr = ANDSWri %3, 0, implicit-def $nzcv
+    %5:gpr32 = CSELWr %3, %4, 0, implicit $nzcv
+    RET_ReallyLR
+
+...
+