[llvm] [NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (PR #98551)

[via llvm-commits]

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@@ -82,45 +153,139 @@ define void @generic_volatile(ptr %a, ptr %b, ptr %c, ptr %d) local_unnamed_addr
   ; CHECK: st.volatile.f64 [%rd{{[0-9]+}}], %fd{{[0-9]+}}
   store volatile double %f.add, ptr %c
 
+  ; TODO: volatile, atomic, and volatile atomic memory operations on vector types.
+  ; Currently, LLVM:
+  ; - does not allow atomic operations on vectors.
+  ; - it allows volatile operations but not clear what that means.
+  ; Following both semantics make sense in general and PTX supports both:
+  ; - volatile/atomic/volatile atomic applies to the whole vector
+  ; - volatile/atomic/volatile atomic applies elementwise
+  ; Actions required:
+  ; - clarify LLVM semantics for volatile on vectors and align the NVPTX backend with those
+  ;   Below tests show that the current implementation picks the semantics in an inconsistent way
+  ;   * volatile <2 x i8> lowers to "elementwise volatile"
+  ;   * <4 x i8> lowers to "full vector volatile"
+  ; - provide support for vector atomics, e.g., by extending LLVM IR or via intrinsics
+  ; - update tests in load-store-sm70.ll as well.
+
+  ; TODO: make this operation consistent with the one for <4 x i8>
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gonzalobg wrote:

Thanks for the hint and for the link to that PR. 
I don't know what's the best way to address this, but will explore and will let you know.

https://github.com/llvm/llvm-project/pull/98551