[llvm] [NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (PR #98551)
Artem Belevich via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 31 11:15:21 PDT 2024
================
@@ -714,21 +715,30 @@ static unsigned int getCodeAddrSpace(MemSDNode *N) {
return NVPTX::PTXLdStInstCode::GENERIC;
}
-static unsigned int getCodeMemorySemantic(MemSDNode *N,
- const NVPTXSubtarget *Subtarget) {
+namespace {
+
+struct OperationOrderings {
+ NVPTX::OrderingUnderlyingType InstrOrdering;
+ NVPTX::OrderingUnderlyingType FenceOrdering;
+ OperationOrderings(NVPTX::Ordering O = NVPTX::Ordering::NotAtomic,
+ NVPTX::Ordering F = NVPTX::Ordering::NotAtomic)
----------------
Artem-B wrote:
Names look a bit inconsistent. Change to IO/FO? Or _InstrOrdering/_FenceOrdering?
https://github.com/llvm/llvm-project/pull/98551
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