[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[Sam Tebbs via llvm-commits]

================
@@ -7985,6 +7985,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
     return;
   }
   case Intrinsic::experimental_vector_partial_reduce_add: {
+
+    if (!TLI.shouldExpandPartialReductionIntrinsic(&I)) {
----------------
SamTebbs33 wrote:

I'm not sure what the reasoning was but I will look into creating an SDNode for this purpose. I do think it would be cleaner to have a default expansion and allow targets to lower it themselves.

https://github.com/llvm/llvm-project/pull/101010