[llvm] [AArch64] Add lowering for `@llvm.experimental.vector.compress` (PR #101015)

[Lawrence Benson via llvm-commits]

lawben wrote:

> For i8/i16 would it be possibly to expand the vectors to multiple i32 vectors, perform the compact, then shrink the result down again? It might not be the prettiest/fastest code, but should hopefully allow them to be supported.

@davemgreen  I'm working on this right now. For i8/i16 vectors with 2 or 4 elements, this is trivial, as we can just extend the "container" vector. For vectors with more elements, e.g., `<vscale x 16 x i8>` I'm trying to convert this to `<vscale x 16 x i32>` and then let `DAGTypeLegalizer::SplitVecRes_VECTOR_COMPRESS` handle the illegal type again. But I'm stuck here a bit. After returning a `VECTOR_COMPRESS` with a `16 x i32` vector from the custom lowering, the next step tries to expand this, which fails for scalable vectors. 

Is there a way to "ignore" this for now and let it get legalized first, which contains the logic for recursively splitting and merging large vectors with `VECTOR_COMPRESS`? 

https://github.com/llvm/llvm-project/pull/101015