[llvm] [GlobalIsel][AArch64] Replace N bit G_ADD with N/2 bit G_ADD if the lower bits are known to be zeros (PR #101327)

[Thorsten Schütt via llvm-commits]

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@@ -5099,6 +5099,69 @@ bool CombinerHelper::matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo) {
   return true;
 }
 
+bool CombinerHelper::matchAddWithKnownZeroLowerHalfBits(MachineInstr &MI,
+                                                        BuildFnTy &MatchInfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_ADD);
+
+  const Register DstReg = MI.getOperand(0).getReg();
+  const LLT DstTy = MRI.getType(DstReg);
+
+  if (!DstTy.isScalar()) {
+    return false;
+  }
+
+  const std::uint64_t FullSize = DstTy.getSizeInBits();
+  const std::uint64_t HalfSize = (FullSize + 1) / 2;
+
+  MachineFunction &MF = *MI.getMF();
+  const DataLayout &DL = MF.getDataLayout();
+
+  if (DL.isLegalInteger(FullSize) || !DL.isLegalInteger(HalfSize)) {
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tschuett wrote:

No braces

https://github.com/llvm/llvm-project/pull/101327