[llvm] 22ce333 - Revert "[DAG][NFC] Use SDPatternMatch for VScale in some instances"

[Michael Maitland via llvm-commits]

Author: Michael Maitland
Date: 2024-07-31T04:55:13-07:00
New Revision: 22ce33304ef9af9e773ac606670ed93944da2c65

URL: https://github.com/llvm/llvm-project/commit/22ce33304ef9af9e773ac606670ed93944da2c65
DIFF: https://github.com/llvm/llvm-project/commit/22ce33304ef9af9e773ac606670ed93944da2c65.diff

LOG: Revert "[DAG][NFC] Use SDPatternMatch for VScale in some instances"

This reverts commit d2304427cb0270259bc083a3db27413823f56e59.

The m_Add and m_Mul are commutative but the code does not expect the
communtativity.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b35d08b327ef3..060e66175d965 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1086,9 +1086,10 @@ bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
   // (load/store (add/sub (add x, y), vscale))
   // (load/store (add/sub (add x, y), (lsl vscale, C)))
   // (load/store (add/sub (add x, y), (mul vscale, C)))
-  if (sd_match(N1, m_AnyOf(m_VScale(m_Value()),
-                           m_Shl(m_VScale(m_Value()), m_ConstInt()),
-                           m_Mul(m_VScale(m_Value()), m_ConstInt()))) &&
+  if ((N1.getOpcode() == ISD::VSCALE ||
+       ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) &&
+        N1.getOperand(0).getOpcode() == ISD::VSCALE &&
+        isa<ConstantSDNode>(N1.getOperand(1)))) &&
       N1.getValueType().getFixedSizeInBits() <= 64) {
     int64_t ScalableOffset = N1.getOpcode() == ISD::VSCALE
                                  ? N1.getConstantOperandVal(0)
@@ -2974,7 +2975,8 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
   }
 
   // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
-  if (sd_match(N0, m_Add(m_Value(), m_VScale(m_Value()))) &&
+  if (N0.getOpcode() == ISD::ADD &&
+      N0.getOperand(1).getOpcode() == ISD::VSCALE &&
       N1.getOpcode() == ISD::VSCALE) {
     const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
     const APInt &VS1 = N1->getConstantOperandAPInt(0);