[llvm] 50cf413 - [X86, CodeGen] Return the correct condition code for SETZUCC

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-07-31T14:09:08+08:00
New Revision: 50cf413426805d32c19c71756f601c864dd6fa7a

URL: https://github.com/llvm/llvm-project/commit/50cf413426805d32c19c71756f601c864dd6fa7a
DIFF: https://github.com/llvm/llvm-project/commit/50cf413426805d32c19c71756f601c864dd6fa7a.diff

LOG: [X86,CodeGen] Return the correct condition code for SETZUCC

llvm-issue: https://github.com/llvm/llvm-project/issues/101288

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrInfo.cpp
    llvm/test/CodeGen/X86/apx/setzucc.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 918a6089fe9a4..7fc786b1e570b 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3121,9 +3121,9 @@ bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
 
 int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
   unsigned Opcode = MCID.getOpcode();
-  if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode) ||
-        X86::isCFCMOVCC(Opcode) || X86::isCCMPCC(Opcode) ||
-        X86::isCTESTCC(Opcode)))
+  if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
+        X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
+        X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
     return -1;
   // Assume that condition code is always the last use operand.
   unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
@@ -3145,8 +3145,9 @@ X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
 }
 
 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
-  return X86::isSETCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
-                                      : X86::COND_INVALID;
+  return X86::isSETCC(MI.getOpcode()) || X86::isSETZUCC(MI.getOpcode())
+             ? X86::getCondFromMI(MI)
+             : X86::COND_INVALID;
 }
 
 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {

diff  --git a/llvm/test/CodeGen/X86/apx/setzucc.ll b/llvm/test/CodeGen/X86/apx/setzucc.ll
index 1436d396bd077..084e54235330c 100644
--- a/llvm/test/CodeGen/X86/apx/setzucc.ll
+++ b/llvm/test/CodeGen/X86/apx/setzucc.ll
@@ -46,3 +46,46 @@ define i64 @i64(i64 %x) nounwind {
   %if = select i1 %t0, i64 1, i64 0
   ret i64 %if
 }
+
+define i32 @flags_copy_lowering() nounwind {
+; CHECK-LABEL: flags_copy_lowering:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB4_1: # %bb1
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    addl %edx, 0
+; CHECK-NEXT:    setb %sil
+; CHECK-NEXT:    adcl $0, %ecx
+; CHECK-NEXT:    testb %sil, %sil
+; CHECK-NEXT:    setzune %dl
+; CHECK-NEXT:    testb %sil, %sil
+; CHECK-NEXT:    je .LBB4_3
+; CHECK-NEXT:  # %bb.2: # %bb1
+; CHECK-NEXT:    # in Loop: Header=BB4_1 Depth=1
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    jne .LBB4_1
+; CHECK-NEXT:  .LBB4_3: # %bb2
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retq
+bb:
+  br label %bb1
+
+bb1:
+  %phi = phi i32 [ 0, %bb ], [ %zext, %bb1 ]
+  %phi2 = phi i32 [ 0, %bb ], [ %add3, %bb1 ]
+  %load = load i32, ptr null, align 4
+  %add = add i32 %load, %phi
+  store i32 %add, ptr null, align 4
+  %icmp = icmp ugt i32 %phi, %add
+  %zext = zext i1 %icmp to i32
+  %add3 = add i32 %phi2, %zext
+  %icmp4 = icmp ult i32 %phi2, 0
+  %and = and i1 %icmp, false
+  br i1 %and, label %bb1, label %bb2
+
+bb2:
+  ret i32 0
+}