[llvm] 8a4b095 - [RISCV][TLI/TTI] Reject scalable offsets in isLegalAddressing mode

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-07-30T12:04:23-07:00
New Revision: 8a4b0954030be3a6e81b098d4e3a1f87ded151b9

URL: https://github.com/llvm/llvm-project/commit/8a4b0954030be3a6e81b098d4e3a1f87ded151b9
DIFF: https://github.com/llvm/llvm-project/commit/8a4b0954030be3a6e81b098d4e3a1f87ded151b9.diff

LOG: [RISCV][TLI/TTI] Reject scalable offsets in isLegalAddressing mode

None of our addressing modes support a scalable offset.  I could not
figure out how to get LSR to actually try such a formula, but let's
be defensive and explicitly prevent this case from being considered
a valid address mode match.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e5460bff6a0ce..f312aed34b8a7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1835,6 +1835,10 @@ bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
   if (AM.BaseGV)
     return false;
 
+  // None of our addressing modes allows a scalable offset
+  if (AM.ScalableOffset)
+    return false;
+
   // RVV instructions only support register addressing.
   if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
     return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs;