[llvm] [GISEL][RISCV] RegBank Scalable Vector Load/Store (PR #99932)

[Michael Maitland via llvm-commits]

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@@ -333,10 +339,16 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   }
   case TargetOpcode::G_STORE: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-    OpdsMapping[0] = GPRValueMapping;
+    TypeSize Size = Ty.getSizeInBits();
+    if (Ty.isVector())
+      OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
+    else
+      OpdsMapping[0] = GPRValueMapping;
+
     OpdsMapping[1] = GPRValueMapping;
     // Use FPR64 for s64 stores on rv32.
-    if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+    if (!Ty.isVector() && GPRSize == 32 &&
+        Ty.getSizeInBits().getFixedValue() == 64) {
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michaelmaitland wrote:

Size.getFixedValue()

https://github.com/llvm/llvm-project/pull/99932