[llvm] [GISEL][RISCV] RegBank Scalable Vector Load/Store (PR #99932)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 30 11:06:23 PDT 2024
================
@@ -310,10 +310,17 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (Opc) {
case TargetOpcode::G_LOAD: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- OpdsMapping[0] = GPRValueMapping;
- OpdsMapping[1] = GPRValueMapping;
+ TypeSize Size = Ty.getSizeInBits();
+ if (Ty.isVector()) {
+ OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
+ OpdsMapping[1] = getVRBValueMapping(Size.getKnownMinValue());
----------------
topperc wrote:
OpsMapping[1] should always be GPRValueMapping
https://github.com/llvm/llvm-project/pull/99932
More information about the llvm-commits
mailing list