[llvm] [GISEL][RISCV] RegBank Scalable Vector Load/Store (PR #99932)

[Craig Topper via llvm-commits]

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@@ -310,10 +310,17 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   switch (Opc) {
   case TargetOpcode::G_LOAD: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-    OpdsMapping[0] = GPRValueMapping;
-    OpdsMapping[1] = GPRValueMapping;
+    TypeSize Size = Ty.getSizeInBits();
+    if (Ty.isVector()) {
+      OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
+      OpdsMapping[1] = getVRBValueMapping(Size.getKnownMinValue());
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topperc wrote:

OpsMapping[1] should always be GPRValueMapping

https://github.com/llvm/llvm-project/pull/99932