[llvm] [RISCV] Adjust RVV stack alignment by ABI (PR #101002)

[Craig Topper via llvm-commits]

topperc wrote:

> > If we're ok with reducing the element width for spilling, do we already have code that does so? I realise we only need to reduce the element width to at most 32bits for E, not all the way down to 8bits. Maybe we only need this code in a strict alignment mode.
> 
> IIUC, we don't do it currently.

Spills use 8 bit element type because that's the only EEW supported for whole register store. Reloads are using vl1re8.v I think.

The objects being processed here aren't just spills though. They are contain scalable vector allocas.

https://github.com/llvm/llvm-project/pull/101002