[llvm] Scalarize the vector inputs to llvm.lround intrinsic by default. (PR #101054)
Sumanth Gundapaneni via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 30 08:39:30 PDT 2024
================
@@ -1034,3 +1037,507 @@ entry:
ret i32 %res
}
+define <2 x float> @intrinsic_fround_v2f32_v2f32(<2 x float> %arg) {
+; GFX9-SDAG-LABEL: intrinsic_fround_v2f32_v2f32:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v2, v0
+; GFX9-SDAG-NEXT: v_sub_f32_e32 v3, v0, v2
+; GFX9-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[4:5]
+; GFX9-SDAG-NEXT: s_brev_b32 s6, -2
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s6, v3, v0
+; GFX9-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v2, v1
+; GFX9-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; GFX9-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[4:5]
+; GFX9-SDAG-NEXT: v_bfi_b32 v1, s6, v3, v1
+; GFX9-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_fround_v2f32_v2f32:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v0
+; GFX9-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
+; GFX9-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[4:5]
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v3
+; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v1
+; GFX9-GISEL-NEXT: v_sub_f32_e32 v3, v1, v2
+; GFX9-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[4:5]
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, v4, v3
+; GFX9-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_fround_v2f32_v2f32:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v2, v0
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v3, v1
+; GFX10-SDAG-NEXT: v_sub_f32_e32 v4, v0, v2
+; GFX10-SDAG-NEXT: v_sub_f32_e32 v5, v1, v3
+; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v4|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s4
+; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v5|, 0.5
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s4
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX10-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
+; GFX10-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_fround_v2f32_v2f32:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v2, v0
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v3, v1
+; GFX10-GISEL-NEXT: v_sub_f32_e32 v4, v0, v2
+; GFX10-GISEL-NEXT: v_sub_f32_e32 v5, v1, v3
+; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v4|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s4
+; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v5|, 0.5
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s4
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v5
+; GFX10-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_fround_v2f32_v2f32:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v2, v0
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v3, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_dual_sub_f32 v4, v0, v2 :: v_dual_sub_f32 v5, v1, v3
+; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v4|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s0
+; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v5|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v4, v0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v1
+; GFX11-SDAG-NEXT: v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_fround_v2f32_v2f32:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v2, v0
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v3, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_dual_sub_f32 v4, v0, v2 :: v_dual_sub_f32 v5, v1, v3
+; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v4|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s0
+; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v5|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v4
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v5
+; GFX11-GISEL-NEXT: v_dual_add_f32 v0, v2, v0 :: v_dual_add_f32 v1, v3, v1
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %0 = tail call <2 x float> @llvm.round.v2f32.v2f32(<2 x float> %arg)
----------------
sgundapa wrote:
Sure. I do not see llvm.round being tested for AMDGPU, but I do understand that should be done in a different patch.
https://github.com/llvm/llvm-project/pull/101054
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