[llvm] [AArch64] Add lowering for `@llvm.experimental.vector.compress` (PR #101015)

[Lawrence Benson via llvm-commits]

lawben wrote:

So it seems I misunderstood the [`st1w` instruction](https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/ST1W--scalar-plus-immediate--single-register---Contiguous-store-words-from-vector--immediate-index--). I thought the "contiguous store" is a "compressing" store. But that does not seem the be the case. So all the paths that do a masked store with `isCompressing=true` are wrong. Sorry :( 

I'll fix this and convert this PR back to a normal one once it is fixed. But it looks like we can only use `compact` for 32 and 64 bit elements. That will shrink the PR by quite a bit. 

https://github.com/llvm/llvm-project/pull/101015