[llvm] [RISCV] Fix vmerge.vvm/vmv.v.v getting folded into ops with mismatching EEW (PR #101152)

[Philip Reames via llvm-commits]

================
@@ -3855,11 +3855,19 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
   // If we end up changing the VL or mask of True, then we need to make sure it
   // doesn't raise any observable fp exceptions, since changing the active
   // elements will affect how fflags is set.
-  if (TrueVL != VL || !IsMasked)
+  if (TrueVL != VL || !IsMasked) {
----------------
preames wrote:

I don't think this is specific to the change case.  Even if we have exactly equal VL values, those values describe a different number of *bits*.  So folding away the vmerge.vv and vmv.v.v is still illegal.

I think you can also use a much easier check here - the VT of the TrueOp should equal the VT of the vmerge or vmv.v.v.  (Really the respective operand, but we don't have widening or narrowing versions of either so that's equivalent.)  

https://github.com/llvm/llvm-project/pull/101152