[llvm] Intrinsic: introduce minimumnum and maximumnum for IR and SelectionDAG (PR #96649)

[YunQiang Su via llvm-commits]

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@@ -8599,23 +8600,33 @@ SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *Node,
     SDValue MinMaxQuiet = DAG.getNode(ISD::FADD, DL, VT, MinMax, MinMax, Flags);
     MinMax =
         DAG.getSelectCC(DL, MinMax, MinMax, MinMaxQuiet, MinMax, ISD::SETUO);
-    //}
   }
 
   // Fixup signed zero behavior.
   if (Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros() ||
       DAG.isKnownNeverZeroFloat(LHS) || DAG.isKnownNeverZeroFloat(RHS)) {
     return MinMax;
   } else {
+    SDValue LRound = LHS;
+    SDValue RRound = RHS;
+    EVT RCCVT = CCVT;
+    // expandIS_FPCLASS is buggy for GPR32+FPR64. Let's round them to single for this case.
+    if (TT.isArch32Bit() && !isOperationLegalOrCustom(ISD::IS_FPCLASS, VT) && VT.getSizeInBits() > TT.getArchPointerBitWidth() && !TT.isX32()) {
+      LRound = DAG.getNode(ISD::FP_ROUND, DL, MVT::f32, LHS,
+                    DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
+      RRound = DAG.getNode(ISD::FP_ROUND, DL, MVT::f32, RHS,
+                    DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
+      RCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
+    }
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wzssyqa wrote:

> The actual condition would more be the integer bitcast of the FP type is not legal
Yes.

> Do not add target checks or workarounds to this code
Another consideration of this condition test is that `expandIS_FPCLASS +0/-0` is too heavy for us. 
We only need to know is the sign bit, while expandIS_FPCLASS will compare with all of the bits with +0/-0.

https://github.com/llvm/llvm-project/pull/96649