[llvm] [RISCV] Qualify all XCV predicates with !is64Bit. (PR #101074)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 12:55:08 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/101074
The tablegen patterns all have isRV32. I did not check if any of them could naively support RV64.
Fixes #101067 and probably other bugs like it we haven't found yet.
Not sure how valuable adding a test case is given that it would only be testing one or two of the places I touched.
>From 33eba10548577b347589a1875f81a3f7e3126de1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 29 Jul 2024 12:52:11 -0700
Subject: [PATCH] [RISCV] Qualify all XCV predicates with !is64Bit.
The tablegen patterns all have isRV32. I did not check if any of
them could naively support RV64.
Fixes #101067 and probably other bugs like it we haven't found yet.
Not sure how value the one test case is given that it would only
be testing one or two of the places I touched.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 27 ++++++++++---------
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 01b2bc08d3ba0..d08430ca5ecfc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1540,7 +1540,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
if (tryIndexedLoad(Node))
return;
- if (Subtarget->hasVendorXCVmem()) {
+ if (Subtarget->hasVendorXCVmem() && !Subtarget->is64Bit()) {
// We match post-incrementing load here
LoadSDNode *Load = cast<LoadSDNode>(Node);
if (Load->getAddressingMode() != ISD::POST_INC)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9ce669a3122f5..42873d4511a10 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -250,14 +250,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (RV64LegalI32 && Subtarget.is64Bit())
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
- if (!Subtarget.hasVendorXCValu())
- setCondCodeAction(ISD::SETLE, XLenVT, Expand);
setCondCodeAction(ISD::SETGT, XLenVT, Custom);
setCondCodeAction(ISD::SETGE, XLenVT, Expand);
- if (!Subtarget.hasVendorXCValu())
- setCondCodeAction(ISD::SETULE, XLenVT, Expand);
setCondCodeAction(ISD::SETUGT, XLenVT, Custom);
setCondCodeAction(ISD::SETUGE, XLenVT, Expand);
+ if (!(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) {
+ setCondCodeAction(ISD::SETULE, XLenVT, Expand);
+ setCondCodeAction(ISD::SETLE, XLenVT, Expand);
+ }
if (RV64LegalI32 && Subtarget.is64Bit())
setOperationAction(ISD::SETCC, MVT::i32, Promote);
@@ -343,7 +343,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.is64Bit())
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Custom);
- } else if (Subtarget.hasVendorXCVbitmanip()) {
+ } else if (Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit()) {
setOperationAction(ISD::ROTL, XLenVT, Expand);
} else {
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
@@ -366,7 +366,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
: Expand);
- if (Subtarget.hasVendorXCVbitmanip()) {
+ if (Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit()) {
setOperationAction(ISD::BITREVERSE, XLenVT, Legal);
} else {
// Zbkb can use rev8+brev8 to implement bitreverse.
@@ -387,14 +387,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
else
setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
}
- } else if (!Subtarget.hasVendorXCVbitmanip()) {
+ } else if (!(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand);
if (RV64LegalI32 && Subtarget.is64Bit())
setOperationAction({ISD::CTTZ, ISD::CTPOP}, MVT::i32, Expand);
}
if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
- Subtarget.hasVendorXCVbitmanip()) {
+ (Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
// We need the custom lowering to make sure that the resulting sequence
// for the 32bit case is efficient on 64bit targets.
if (Subtarget.is64Bit()) {
@@ -1439,7 +1439,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
}
- if (Subtarget.hasVendorXCVmem()) {
+ if (Subtarget.hasVendorXCVmem() && !Subtarget.is64Bit()) {
setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
@@ -1449,7 +1449,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
}
- if (Subtarget.hasVendorXCValu()) {
+ if (Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()) {
setOperationAction(ISD::ABS, XLenVT, Legal);
setOperationAction(ISD::SMIN, XLenVT, Legal);
setOperationAction(ISD::UMIN, XLenVT, Legal);
@@ -1928,12 +1928,13 @@ bool RISCVTargetLowering::signExtendConstant(const ConstantInt *CI) const {
}
bool RISCVTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
- return Subtarget.hasStdExtZbb() || Subtarget.hasVendorXCVbitmanip();
+ return Subtarget.hasStdExtZbb() ||
+ (Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit());
}
bool RISCVTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
return Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
- Subtarget.hasVendorXCVbitmanip();
+ (Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit());
}
bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
@@ -21082,7 +21083,7 @@ bool RISCVTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const {
- if (Subtarget.hasVendorXCVmem()) {
+ if (Subtarget.hasVendorXCVmem() && !Subtarget.is64Bit()) {
if (Op->getOpcode() != ISD::ADD)
return false;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index a61a9f10be86c..4cd904c039a98 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -280,7 +280,7 @@ bool RISCVTTIImpl::hasActiveVectorLength(unsigned, Type *DataTy, Align) const {
TargetTransformInfo::PopcntSupportKind
RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
- return ST->hasStdExtZbb() || ST->hasVendorXCVbitmanip()
+ return ST->hasStdExtZbb() || (ST->hasVendorXCVbitmanip() && !ST->is64Bit())
? TTI::PSK_FastHardware
: TTI::PSK_Software;
}
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