[llvm] [AMDGPU] Always lower s/udiv64 by constant to MUL (PR #100723)

[Matt Arsenault via llvm-commits]

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@@ -6405,7 +6405,12 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
     if (VT.isVector())
       WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
                                 VT.getVectorElementCount());
-    if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
+    // Some targets like AMDGPU try to go from SDIV to SDIVREM which is then
+    // custom lowered. This is very expensive so avoid it at all costs for
+    // constant divisors.
+    if ((isOperationExpand(ISD::SDIV, VT) &&
+         isOperationCustom(ISD::SDIVREM, VT.getScalarType())) ||
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arsenm wrote:

This logic probably isn't exactly right; it probably shouldn't be looking at the scalar type for no reason. However the DAG legalization rules don't really let you figure out if a vector operation is going to be scalarized or not 

https://github.com/llvm/llvm-project/pull/100723