[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[via llvm-commits]

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git-clang-format --diff c7a3346ab6a8fbd551a80bd4028ec8624daa35e4 955c84e7aa1f811f2a78585d9dbf985672d3e21e --extensions h,cpp -- llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8cf997cf0a..81bd786854 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1985,9 +1985,11 @@ bool AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(
 
   auto RetScalarTy = RetTy->getScalarType();
   if (RetScalarTy->isIntegerTy(64))
-    InputTy = VectorType::get(Type::getInt16Ty(I->getContext()), 8, RetTy->isScalableTy());
+    InputTy = VectorType::get(Type::getInt16Ty(I->getContext()), 8,
+                              RetTy->isScalableTy());
   else if (RetScalarTy->isIntegerTy(32))
-    InputTy = VectorType::get(Type::getInt8Ty(I->getContext()), 16, RetTy->isScalableTy());
+    InputTy = VectorType::get(Type::getInt8Ty(I->getContext()), 16,
+                              RetTy->isScalableTy());
   else
     return true;
 

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https://github.com/llvm/llvm-project/pull/101010