[llvm] [AMDGPU] Correctly insert s_nops for implicit read of SDWA (PR #100276)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 10:34:40 PDT 2024
================
@@ -875,13 +875,34 @@ GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def,
return DataIdx >= 0 &&
TRI->regsOverlap(MI.getOperand(DataIdx).getReg(), Reg);
};
+
int WaitStatesNeededForDef =
VALUWaitStates - getWaitStatesSince(IsHazardFn, VALUWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
return WaitStatesNeeded;
}
+static const MachineOperand *
+getDstSelForwardingOperand(const MachineInstr &MI, const GCNSubtarget &ST) {
+ if (!SIInstrInfo::isVALU(MI))
+ return nullptr;
+
+ const SIInstrInfo *TII = ST.getInstrInfo();
+ if (SIInstrInfo::isSDWA(MI)) {
+ if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel))
+ if (DstSel->getImm() == AMDGPU::SDWA::DWORD)
+ return nullptr;
+ } else {
+ if (!AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::op_sel) ||
+ !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm() &
+ SISrcMods::DST_OP_SEL))
+ return nullptr;
+ }
----------------
arsenm wrote:
Given all the repurposed uses of op_sel, this is a bit coarse. I think the function needs a comment about what this is detecting.
Also, does this only matter if ECC is enabled? Since we don't have a great situation for tracking partial register writes, should it just consider any access to the register as the write?
https://github.com/llvm/llvm-project/pull/100276
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