[llvm] [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, c2+c3), c3). (PR #100966)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

> > Do you mean to expand sign_extend_inreg X, i16 into (X << 48) s>> 48 in DAGCombine?
> 
> I wouldn't want to expand sign_extend_inreg by itself.
> 
> But maybe we should expand this into a sra+shl during DAGCombine.
> 
> ```
>         t20: i64 = sign_extend_inreg t19, ValueType:ch:i16
>       t21: i64 = sra t20, Constant:i64<15>
> ```

I filed https://github.com/llvm/llvm-project/issues/101040 to track this issue.


https://github.com/llvm/llvm-project/pull/100966