[llvm] 1b4be6a - [ARM] Regenerate vselect_imax.ll
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 07:54:06 PDT 2024
Author: Simon Pilgrim
Date: 2024-07-29T15:53:42+01:00
New Revision: 1b4be6a474b3747765a218201bd637f899fd9b66
URL: https://github.com/llvm/llvm-project/commit/1b4be6a474b3747765a218201bd637f899fd9b66
DIFF: https://github.com/llvm/llvm-project/commit/1b4be6a474b3747765a218201bd637f899fd9b66.diff
LOG: [ARM] Regenerate vselect_imax.ll
Added:
Modified:
llvm/test/CodeGen/ARM/vselect_imax.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/vselect_imax.ll b/llvm/test/CodeGen/ARM/vselect_imax.ll
index 37f511fcc68cc..9f0edb7117bd1 100644
--- a/llvm/test/CodeGen/ARM/vselect_imax.ll
+++ b/llvm/test/CodeGen/ARM/vselect_imax.ll
@@ -1,9 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes='print<cost-model>' -mtriple=arm-apple-ios6.0.0 -mcpu=cortex-a8 2>&1 -disable-output | FileCheck %s --check-prefix=COST
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; Make sure that ARM backend with NEON handles vselect.
define void @vmax_v4i32(ptr %m, <4 x i32> %a, <4 x i32> %b) {
-; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+; CHECK-LABEL: vmax_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vldr d17, [sp]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
+; CHECK-NEXT: mov pc, lr
%cmpres = icmp sgt <4 x i32> %a, %b
%maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b
store <4 x i32> %maxres, ptr %m
@@ -12,51 +21,84 @@ define void @vmax_v4i32(ptr %m, <4 x i32> %a, <4 x i32> %b) {
%T0_10 = type <16 x i16>
%T1_10 = type <16 x i1>
+define void @func_blend10(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend10:
-define void @func_blend10(ptr %loadaddr, ptr %loadaddr2,
- ptr %blend, ptr %storeaddr) {
- %v0 = load %T0_10, ptr %loadaddr
- %v1 = load %T0_10, ptr %loadaddr2
- %c = icmp slt %T0_10 %v0, %v1
-; CHECK: vmin.s16
-; CHECK: vmin.s16
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.16 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vmin.s16 q8, q9, q8
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1:128]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: vmin.s16 q9, q9, q10
+; CHECK-NEXT: vst1.16 {d16, d17}, [r3:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]
+; CHECK-NEXT: mov pc, lr
; COST: func_blend10
; COST: cost of 0 {{.*}} icmp
; COST: cost of 4 {{.*}} select
+
+ %v0 = load %T0_10, ptr %loadaddr
+ %v1 = load %T0_10, ptr %loadaddr2
+ %c = icmp slt %T0_10 %v0, %v1
%r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1
store %T0_10 %r, ptr %storeaddr
ret void
}
+
%T0_14 = type <8 x i32>
%T1_14 = type <8 x i1>
+define void @func_blend14(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend14:
-define void @func_blend14(ptr %loadaddr, ptr %loadaddr2,
- ptr %blend, ptr %storeaddr) {
- %v0 = load %T0_14, ptr %loadaddr
- %v1 = load %T0_14, ptr %loadaddr2
- %c = icmp slt %T0_14 %v0, %v1
-; CHECK: vmin.s32
-; CHECK: vmin.s32
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.32 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vmin.s32 q8, q9, q8
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1:128]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: vmin.s32 q9, q9, q10
+; CHECK-NEXT: vst1.32 {d16, d17}, [r3:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]
+; CHECK-NEXT: mov pc, lr
; COST: func_blend14
; COST: cost of 0 {{.*}} icmp
; COST: cost of 4 {{.*}} select
+ %v0 = load %T0_14, ptr %loadaddr
+ %v1 = load %T0_14, ptr %loadaddr2
+ %c = icmp slt %T0_14 %v0, %v1
%r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1
store %T0_14 %r, ptr %storeaddr
ret void
}
+
%T0_15 = type <16 x i32>
%T1_15 = type <16 x i1>
+define void @func_blend15(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend15:
-define void @func_blend15(ptr %loadaddr, ptr %loadaddr2,
- ptr %blend, ptr %storeaddr) {
-; CHECK: vmin.s32
-; CHECK: vmin.s32
- %v0 = load %T0_15, ptr %loadaddr
- %v1 = load %T0_15, ptr %loadaddr2
- %c = icmp slt %T0_15 %v0, %v1
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.32 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vmin.s32 q8, q9, q8
+; CHECK-NEXT: vld1.32 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vld1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vmin.s32 q10, q11, q10
+; CHECK-NEXT: vld1.32 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vld1.32 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vmin.s32 q12, q13, q12
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]
+; CHECK-NEXT: vld1.64 {d22, d23}, [r0:128]
+; CHECK-NEXT: vmin.s32 q9, q11, q9
+; CHECK-NEXT: vst1.32 {d16, d17}, [r3:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r3:128]!
+; CHECK-NEXT: vst1.32 {d24, d25}, [r3:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]
+; CHECK-NEXT: mov pc, lr
; COST: func_blend15
; COST: cost of 0 {{.*}} icmp
; COST: cost of 8 {{.*}} select
+
+ %v0 = load %T0_15, ptr %loadaddr
+ %v1 = load %T0_15, ptr %loadaddr2
+ %c = icmp slt %T0_15 %v0, %v1
%r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1
store %T0_15 %r, ptr %storeaddr
ret void
@@ -66,8 +108,7 @@ define void @func_blend15(ptr %loadaddr, ptr %loadaddr2,
; lowering we also need to adjust the cost.
%T0_18 = type <4 x i64>
%T1_18 = type <4 x i1>
-define void @func_blend18(ptr %loadaddr, ptr %loadaddr2,
- ptr %blend, ptr %storeaddr) {
+define void @func_blend18(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend18:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
@@ -118,20 +159,20 @@ define void @func_blend18(ptr %loadaddr, ptr %loadaddr2,
; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: mov pc, lr
- %v0 = load %T0_18, ptr %loadaddr
- %v1 = load %T0_18, ptr %loadaddr2
- %c = icmp slt %T0_18 %v0, %v1
; COST: func_blend18
; COST: cost of 0 {{.*}} icmp
; COST: cost of 21 {{.*}} select
+ %v0 = load %T0_18, ptr %loadaddr
+ %v1 = load %T0_18, ptr %loadaddr2
+ %c = icmp slt %T0_18 %v0, %v1
%r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1
store %T0_18 %r, ptr %storeaddr
ret void
}
+
%T0_19 = type <8 x i64>
%T1_19 = type <8 x i1>
-define void @func_blend19(ptr %loadaddr, ptr %loadaddr2,
- ptr %blend, ptr %storeaddr) {
+define void @func_blend19(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend19:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, lr}
@@ -226,20 +267,20 @@ define void @func_blend19(ptr %loadaddr, ptr %loadaddr2,
; CHECK-NEXT: vst1.64 {d16, d17}, [r3:128]
; CHECK-NEXT: pop {r4, r5, r6, lr}
; CHECK-NEXT: mov pc, lr
- %v0 = load %T0_19, ptr %loadaddr
- %v1 = load %T0_19, ptr %loadaddr2
- %c = icmp slt %T0_19 %v0, %v1
; COST: func_blend19
; COST: cost of 0 {{.*}} icmp
; COST: cost of 54 {{.*}} select
+ %v0 = load %T0_19, ptr %loadaddr
+ %v1 = load %T0_19, ptr %loadaddr2
+ %c = icmp slt %T0_19 %v0, %v1
%r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1
store %T0_19 %r, ptr %storeaddr
ret void
}
+
%T0_20 = type <16 x i64>
%T1_20 = type <16 x i1>
-define void @func_blend20(ptr %loadaddr, ptr %loadaddr2,
- ptr %blend, ptr %storeaddr) {
+define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend20:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
@@ -435,12 +476,12 @@ define void @func_blend20(ptr %loadaddr, ptr %loadaddr2,
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: mov pc, lr
- %v0 = load %T0_20, ptr %loadaddr
- %v1 = load %T0_20, ptr %loadaddr2
- %c = icmp slt %T0_20 %v0, %v1
; COST: func_blend20
; COST: cost of 0 {{.*}} icmp
; COST: cost of 108 {{.*}} select
+ %v0 = load %T0_20, ptr %loadaddr
+ %v1 = load %T0_20, ptr %loadaddr2
+ %c = icmp slt %T0_20 %v0, %v1
%r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1
store %T0_20 %r, ptr %storeaddr
ret void
More information about the llvm-commits
mailing list