[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 07:46:13 PDT 2024
================
@@ -1971,6 +1971,57 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
return false;
}
+bool AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(
+ const CallInst *CI) const {
+ const bool TargetLowers = false;
+ const bool GenericLowers = true;
+
+ auto *I = dyn_cast<IntrinsicInst>(CI);
+ if (!I)
+ return GenericLowers;
+
+ ScalableVectorType *RetTy = dyn_cast<ScalableVectorType>(I->getType());
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sdesmalen-arm wrote:
Am I right that this is just an artificial limitation at the moment? (i.e. we can make this work for fixed-length vectors too)
https://github.com/llvm/llvm-project/pull/101010
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