[llvm] [AArch64] Add lowering for `@llvm.experimental.vector.compress` (PR #101015)

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git-clang-format --diff 5bd3aef5e285cce793e3fc6b21299ac9d650a947 fb3759fc2c5c2ea84d0a3e99e11310ba0398af4e --extensions h,cpp -- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 6bfeb4d11e..b495b0ebcd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -23123,7 +23123,8 @@ static SDValue combineVECTOR_COMPRESSStore(SelectionDAG &DAG,
 
   // If the passthru is all 0s, we don't need an explicit passthru store.
   unsigned MinElmts = VecVT.getVectorMinNumElements();
-  if (ISD::isConstantSplatVectorAllZeros(Passthru.getNode()) && (MinElmts == 2 || MinElmts == 4))
+  if (ISD::isConstantSplatVectorAllZeros(Passthru.getNode()) &&
+      (MinElmts == 2 || MinElmts == 4))
     return SDValue();
 
   if (!Passthru.isUndef())

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https://github.com/llvm/llvm-project/pull/101015