[llvm] [SelectionDAG] Simplify vselect true, T, F -> T (PR #100992)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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arsenm wrote:

```suggestion
; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
```

Don't need to add -verify-machineinstrs in any random test 

https://github.com/llvm/llvm-project/pull/100992