[llvm] 5bd3aef - [AMDGPU] Use a generic printer for NamedIntOperands. (#100399)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 01:54:09 PDT 2024
Author: Ivan Kosarev
Date: 2024-07-29T09:54:05+01:00
New Revision: 5bd3aef5e285cce793e3fc6b21299ac9d650a947
URL: https://github.com/llvm/llvm-project/commit/5bd3aef5e285cce793e3fc6b21299ac9d650a947
DIFF: https://github.com/llvm/llvm-project/commit/5bd3aef5e285cce793e3fc6b21299ac9d650a947.diff
LOG: [AMDGPU] Use a generic printer for NamedIntOperands. (#100399)
This includes simplifying printing dmask modifiers where we don't need
to mask the value to print.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Added:
Modified:
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SMInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index c31f85dbea127..a75391fcfa8a4 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -119,20 +119,6 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
}
}
-void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- if (int64_t Offset = MI->getOperand(OpNo).getImm())
- O << " offset0:" << formatDec(Offset);
-}
-
-void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- if (int64_t Offset = MI->getOperand(OpNo).getImm())
- O << " offset1:" << formatDec(Offset);
-}
-
void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -145,13 +131,6 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
O << formatHex(MI->getOperand(OpNo).getImm());
}
-void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " offset:";
- printSMEMOffset(MI, OpNo, STI, O);
-}
-
void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -269,14 +248,6 @@ void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
return;
}
-void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O) {
- if (MI->getOperand(OpNo).getImm()) {
- O << " dmask:";
- printU16ImmOperand(MI, OpNo, STI, O);
- }
-}
-
void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Dim = MI->getOperand(OpNo).getImm();
@@ -678,26 +649,6 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
O << " blgp:" << Imm;
}
-void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- unsigned Imm = MI->getOperand(OpNo).getImm();
- if (!Imm)
- return;
-
- O << " cbsz:" << Imm;
-}
-
-void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- unsigned Imm = MI->getOperand(OpNo).getImm();
- if (!Imm)
- return;
-
- O << " abid:" << Imm;
-}
-
void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -711,30 +662,6 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
O << ", ";
}
-void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_vdst:" << formatDec(MI->getOperand(OpNo).getImm());
-}
-
-void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_va_vdst:" << formatDec(MI->getOperand(OpNo).getImm());
-}
-
-void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_vm_vsrc:" << formatDec(MI->getOperand(OpNo).getImm());
-}
-
-void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_exp:" << formatDec(MI->getOperand(OpNo).getImm());
-}
-
bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
unsigned OpNo) const {
return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
@@ -1127,18 +1054,6 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
}
}
-void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " row_mask:" << formatHex(MI->getOperand(OpNo).getImm());
-}
-
-void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " bank_mask:" << formatHex(MI->getOperand(OpNo).getImm());
-}
-
void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -1782,14 +1697,13 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
O << ' ' << formatDec(Imm);
}
-void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- uint8_t Imm = MI->getOperand(OpNo).getImm();
- if (!Imm)
- return;
-
- O << " byte_sel:" << formatDec(Imm);
+void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O, StringRef Prefix,
+ bool PrintInHex, bool AlwaysPrint) {
+ int64_t V = MI->getOperand(OpNo).getImm();
+ if (AlwaysPrint || V != 0)
+ O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
}
#include "AMDGPUGenAsmWriter.inc"
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
index 4a39022aea7cf..4d44db5d9d818 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
@@ -48,24 +48,16 @@ class AMDGPUInstPrinter : public MCInstPrinter {
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printSMEMOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
- void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCPol(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printTH(const MCInst *MI, int64_t TH, int64_t Scope, raw_ostream &O);
void printScope(int64_t Scope, raw_ostream &O);
- void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -110,10 +102,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printDppRowMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
- void printDppBankMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -154,21 +142,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printWaitVAVDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
- void printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O, unsigned N);
@@ -182,8 +158,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printExpTgt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
- void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
+ void printNamedInt(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O,
+ StringRef Prefix, bool PrintInHex, bool AlwaysPrint);
public:
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 00a8b159c9526..e8a67ab6f7e94 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1015,18 +1015,29 @@ def SDWAVopcDst : BoolRC {
let PrintMethod = "printVOPDst";
}
-class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
+class NamedIntOperand<ValueType Type, string prefix, bit Optional = 1,
string name = NAME>
: CustomOperand<Type, Optional, name> {
+ string Prefix = prefix;
+
let PredicateMethod =
"getPredicate([](const AMDGPUOperand &Op) -> bool { "#
"return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })";
+
string Validator = "[](int64_t V) { return true; }";
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
let ParserMethod =
"[this](OperandVector &Operands) -> ParseStatus { "#
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
"AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }";
+
+ bit PrintInHex = 0;
+ bit AlwaysPrint = 0;
+ let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "
+ "const MCSubtargetInfo &STI, raw_ostream &O) { "
+ "printNamedInt(MI, OpNo, STI, O, \""#Prefix#"\", "#
+ !if(PrintInHex, "true", "false")#", "#
+ !if(AlwaysPrint, "true", "false")#"); }";
}
class NamedBitOperand<string Id, string Name = NAME>
@@ -1065,6 +1076,7 @@ class ArrayOperand0<string Id, string Name = NAME>
let ImmTy = "ImmTyOffset" in
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
+let PrintMethod = "printOffset" in
def Offset : NamedIntOperand<i32, "offset">;
let Validator = "isUInt<8>" in {
def Offset0 : NamedIntOperand<i32, "offset0">;
@@ -1103,6 +1115,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">;
def FORMAT : CustomOperand<i8>;
+let PrintInHex = 1 in
def DMask : NamedIntOperand<i16, "dmask">;
def Dim : CustomOperand<i8, /*optional=*/1>;
@@ -1123,16 +1136,18 @@ def IndexKey8bit : CustomOperand<i32, 1>;
def dpp8 : CustomOperand<i32, 0, "DPP8">;
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
-let DefaultValue = "0xf" in {
+let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1 in {
def DppRowMask : NamedIntOperand<i32, "row_mask">;
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
}
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
+ let PrintMethod = "printDppBoundCtrl";
}
-let DecoderMethod = "decodeDpp8FI" in
+let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
+let PrintMethod = "printDppFI" in
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
def blgp : CustomOperand<i32, 1, "BLGP">;
@@ -1146,6 +1161,7 @@ def hwreg : CustomOperand<i32, 0, "Hwreg">;
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
+let AlwaysPrint = 1 in {
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
let Validator = "isUInt<4>";
}
@@ -1158,6 +1174,7 @@ def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
let Validator = "isUInt<1>";
}
+} // End AlwaysPrint = 1
def ByteSel : NamedIntOperand<i8, "byte_sel"> {
let Validator = "isUInt<2>";
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 3d6e8efc905d5..8cc963a6c1bb5 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -11,7 +11,10 @@ def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
let EncoderMethod = "getSMEMOffsetEncoding",
DecoderMethod = "decodeSMEMOffset" in {
def SMEMOffset : ImmOperand<i32, "SMEMOffset", 1>;
-def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0>;
+def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0> {
+ let AlwaysPrint = 1;
+ let PrintInHex = 1;
+}
def OptSMEMOffsetMod : NamedIntOperand<i32, "offset"> {
let ImmTy = SMEMOffsetMod.ImmTy;
let PredicateMethod = SMEMOffsetMod.PredicateMethod;
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