[llvm] [DAG] Support saturated truncate (PR #99418)

[David Green via llvm-commits]

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@@ -1410,6 +1410,12 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
+  for (MVT VT : {MVT::v8i16, MVT::v4i32}) {
+    setOperationAction(ISD::TRUNCATE_SSAT_S, VT, Custom);
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davemgreen wrote:

Sorry - I'm not sure I understand what you mean. I believe in this version of the code just making them Legal should be fine, but I'm not sure which comment this was referring to or what code to DAG combiner.

https://github.com/llvm/llvm-project/pull/99418