[llvm] [DAG] Support saturated truncate (PR #99418)

[David Green via llvm-commits]

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@@ -1410,6 +1410,12 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
+  for (MVT VT : {MVT::v8i16, MVT::v4i32}) {
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davemgreen wrote:

I think the basics should be this, with the different sat nodes.
```
def : Pat<(v2i32 (truncusat_u (v2i64 V128:$Vn))),
          (UQXTNv2i32 V128:$Vn)>;
```

(There are other "concat" UQXTN2 patterns but the ones above are the basics needed to get things working).

https://github.com/llvm/llvm-project/pull/99418