[llvm] [DAG] Support saturated truncate (PR #99418)

[via llvm-commits]

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@@ -1410,6 +1410,12 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
+  for (MVT VT : {MVT::v8i16, MVT::v4i32}) {
+    setOperationAction(ISD::TRUNCATE_SSAT_S, VT, Custom);
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ParkHanbum wrote:

agree. I also added a comment with that intention and I'm thinking maybe adding code to `DAGCombiner` can solve it. 

do you think I should include this in this patch as well?

https://github.com/llvm/llvm-project/pull/99418