[llvm] [AMDGPU][NFCI] Declare offset0/1 operands to be i64. (PR #100560)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 25 05:56:31 PDT 2024
================
@@ -1270,8 +1270,8 @@ bool AMDGPUDAGToDAGISel::SelectDSReadWrite2(SDValue Addr, SDValue &Base,
// (add n0, c0)
if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) {
Base = N0;
- Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
- Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
+ Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i64);
+ Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i64);
----------------
arsenm wrote:
I'd just use 32-bit for consistency. I doubt DS instructions will ever have offsets this big, it would imply multiplying the encoding size
https://github.com/llvm/llvm-project/pull/100560
More information about the llvm-commits
mailing list